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SLVS585E July 2005 – June 2015 TPS62110 , TPS62111 , TPS62112 , TPS62113

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RSA|16
- MPQF145D

散熱焊盤機械數據 (封裝 | 引腳)

RSA|16
- QFND072M

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage at VIN, VINA	–0.3	20	V
V_I	Voltage at SW	–1	20	V
	Voltage at EN, SYNC, LBO, PG	–0.3	20
	Voltage at LBI, FB	–0.3	7
I_O	Output current at SW		2400	mA
T_J	Maximum junction temperature		150	°C
T_A	Operating free-air temperature	–40	85	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_CC	Supply voltage at VIN, VINA	3.1	17	V
	Maximum voltage at PG, LBO, EN, SYNC		17	V
T_J	Operating junction temperature	–40	125	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS6211x	UNIT
		RSA (VQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	48.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	45.4	°C/W
R_θJB	Junction-to-board thermal resistance	16.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	16.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_I = 12 V, V_O = 3.3 V, I_O = 600 mA, EN = V_I, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY CURRENT
V_I	Input voltage			3.1		17	V
I_(Q)	Operating quiescent current	I_O = 0 mA, SYNC = GND, V_I = 7.2 V, T_A = 25°C ⁽¹⁾			20		µA
I_(Q)	Operating quiescent current	I_O = 0 mA, SYNC = GND, V_I = 17 V ⁽¹⁾			23	26	µA
I_Q(LBI)	Quiescent current with enhanced LBI comparator version (TPS62113 only).	EN = V_I , LBI = GND			10		µA
I_(SD)	Shutdown current	EN = GND			1.5	5	µA
I_(SD)	Shutdown current	EN = GND, T_A = 25°C, V_I = 7.2 V			1.5	3	µA
ENABLE
V_IH	EN high-level input voltage			1.3			V
V_IL	EN low-level input voltage					0.3	V
	EN trip-point hysteresis				170		mV
I_lkg	EN input leakage current	EN = GND or V_I, V_I = 12 V			0.01	0.2	µA
I_(EN)	EN input current	0.6 V ≤ V_(EN) ≤ 4 V			10	20	µA
V_(UVLO)	Undervoltage lockout threshold	Input voltage falling		2.8	3	3.1	V
	Undervoltage lockout hysteresis				250	300	mV
POWER SWITCH
R_DS(ON)	P-channel MOSFET ON-resistance	V_I ≥ 5.4 V; I_O = 350 mA			165	250	mΩ
		V_I = 3.5 V; I_O = 200 mA			340
		V_I = 3 V; I_O = 100 mA			490
I_lkg	P-channel MOSFET leakage current	V_DS = 17 V			0.1	1	µA
I_LIMF	P-channel MOSFET current limit	V_I = 7.2 V, V_O = 3.3 V		2100	2400	2600	mA
R_DS(ON)	N-channel MOSFET ON-resistance	V_I ≥ 5.4 V; I_O = 350 mA			145	200	mΩ
		V_I = 3.5 V; I_O = 200 mA			170
		V_I = 3 V; I_O = 100 mA			200
I_lkg	N-channel MOSFET leakage current	V_DS = 17 V			0.1	2	µA
PG OUTPUT, LBI, LBO
V_(PG)	Power good trip voltage				V_O – 1.6%		V
	Power good delay time	V_O ramping positive			50		µs
	Power good delay time	V_O ramping negative			200		µs
V_OL	PG, LBO output-low voltage	V_(FB)= 0.8 × V_O nominal, I_OL = 1 mA				0.3	V
I_OL	PG, LBO sink current				1		mA
I_lkg	PG, LBO output leakage current	V_(FB) = V_O nominal, V_(LBI) = V_I			0.01	0.25	µA
	Minimum supply voltage for valid power good, LBI, LBO signal				3		V
V_LBI	LBI input trip voltage	Input voltage falling			1.256		V
I_lkg	LBI input leakage current				10	100	nA
	LBI input trip-point accuracy					1.5%
V_LBI,HYS	Low-battery input hysteresis				25		mV
OSCILLATOR
f_S	Oscillator frequency			900	1000	1100	kHz
f_(SYNC)	Synchronization range	CMOS-logic clock signal on SYNC pin		800		1400	kHz
V_IH	SYNC high-level input voltage			1.5			V
V_IL	SYNC low-level input voltage					0.3	V
I_lkg	SYNC input leakage current	SYNC = GND or VIN			0.01	0.2	µA
	SYNC trip-point hysteresis				170		mV
I_lkg	SYNC input leakage current	0.6 V ≤ V_(SYNC) ≤ 4 V			10	20	µA
	Duty cycle of external clock signal			30%		90%
OUTPUT
V_O	Adjustable output voltage range	TPS62110 TPS62113		1.153		16	V
V_FB	Feedback voltage	TPS62110 TPS62113			1.153		V
I_lkg	FB input leakage current	TPS62110 TPS62113			10	100	nA
	Feedback voltage tolerance	TPS62110 TPS62113	V_I = 3.1 V to 17 V; 0 mA < I_O < 1500 mA⁽³⁾	–2%		2%
	Fixed output voltage tolerance⁽²⁾	TPS62111	V_I = 3.8 V to 17 V; 0 mA < I_O < 1500 mA⁽³⁾	–3%		3%
	Fixed output voltage tolerance⁽²⁾	TPS62112	V_I = 5.5 V to 17 V; 0 mA < I_O < 1500 mA⁽³⁾	–3%		3%
I_O	Maximum output current	V_I ≥ 3 V (once undervoltage lockout voltage exceeded)			100		mA
		V_I ≥ 3.5 V			500
		V_I ≥ 4.3 V			1200
		V_I ≥ 6 V			1500
	Current into internal voltage divider for fixed voltage versions				5		µA
η	Efficiency	V_I = 7.2 V; V_O = 3.3 V; I_O = 600 mA			92%
η	Efficiency	V_I = 12 V, V_o = 5 V, I_o = 600 mA			92%
	Duty-cycle range for main switches	at 1 MHz		10%		100%
	Minimum t_on time for main switch			100			ns
T_SD	Shutdown temperature				145		°C
	Start-up time	I_O = 800 mA, V_I = 12 V, V_o = 3.3 V			1		ms

(1) Device is not switching.

(2) The output voltage accuracy includes line and load regulation over the full temperature range T_A = –40°C to 85°C. See No-Load Operation.

(3) The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimum input voltage.

8.6 Typical Characteristics

TPS62110 TPS62111 TPS62112 TPS62113 maxio_v_vi_lvs585.gif

Figure 1. TPS62111 Maximum Output Current vs Input Voltage

TPS62110 TPS62111 TPS62112 TPS62113 quies_v_vi110_lvs585.gif

Figure 3. Quiescent Current vs Input Voltage

TPS62110 TPS62111 TPS62112 TPS62113 sw_fr110_lvs585.gif

Figure 2. Switching Frequency vs Input Voltage