9.3.1 Enable

A logic low on EN forces the TPS6211x devices into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The LBO pin is high impedance, while PG is held low. The supply current is reduced to less than 2 µA in the shutdown mode. When the device is in thermal shutdown, the band gap is forced to be switched on even if the device is set into shutdown by pulling EN to GND.

If an output voltage is present when the device is disabled, which could be due to an external voltage source or a super capacitor, the reverse leakage current is specified under electrical characteristics. Pulling the enable pin high starts up the TPS6211x devices with the soft-start. If the EN pin is connected to any voltage other than V_I or GND, an increased leakage current of typically 10 µA and up to 20 µA can occur. See TPS6211x Driving EN and SYNC Pins (SLVA295) for details.

9.3.2 Low-Battery Detector (Standard Version)

The low-battery output (LBO) is an open-drain type which goes low when the voltage at the low-battery input (LBI) falls below the trip point of 1.256 V ±1.5%. The voltage at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 4. TI recommends the sum of resistors R1 + R2 as well as the sum of resistors R5 + R6 to be in the 100-kΩ to 1-MΩ range for high efficiency at low output current. An external pullup resistor can be connected to V_O, or any other voltage rail in the voltage range of 0 V to 17 V. During start-up, the LBO output signal is invalid for the first 500 µs. LBO is high-impedance when the device is disabled. If the low-battery comparator function is not used, connect LBI to ground. The low-battery detector is disabled when the device is disabled.

When the LBI is used to supervise the battery voltage and shut down the TPS6211x devices at low-input voltages, the battery voltage rises when its current drops to zero. The implemented hysteresis on the LBI pin may not be sufficient for all types of batteries. Figure 4 shows how an additional external hysteresis can be implemented. See Adding Hysteresis to Low-Battery Input on the TPS62113 (SLVA373) for details.

Figure 4. LBI With Increased Hysteresis

9.3.3 Enable/Low-Battery Detector - Enhanced Version (TPS62113 Only)

The TPS62113 device offers an enhanced LBI functionality to provide a precise, user-programmable undervoltage shutdown. No additional supply voltage supervisor (SVS) is needed to provide this function. When the enable (EN) pin is pulled high, only the internal bandgap voltage reference is switched on to provide a reference source for the LBI comparator. As long as the voltage at LBI is less than the LBI trip point, all other internal circuits are shut down, reducing the supply current to 10 µA. As soon as input voltage at LBI rises above the LBI trip point of 1.256 V, the device is completely enabled and starts switching.

This functionality is the only difference between the TPS62110 and TPS62113 devices.

9.3.4 Power Good Comparator

The power good (PG) comparator is an open-drain output capable of sinking 1 mA (typical). The PG is only active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is pulled to GND.

The PG output is only valid after a 250-µs delay when the device is enabled and the supply voltage is greater than the undervoltage lockout V_(UVLO).

The PG pin becomes active-high when the output voltage exceeds 98.4% (typical) of its nominal value. Leave the PG pin floating or grounded when not used.

9.3.5 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit prevents the device from misoperation at low-input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The minimum input voltage to start up the TPS6211x devices is 3.4 V (worst case). The device shuts down at 2.8 V minimum.

9.3.6 Synchronization

If no clock signal is applied, the converter operates with a typical switching frequency of 1 MHz. It is possible to synchronize the converter to an external clock within a frequency range from 0.8 MHz to 1.4 MHz only. The device automatically detects the rising edge of the first clock and synchronizes immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation. The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 6.25 µs if the internal clock has its minimum frequency of 800 kHz.

If the device is synchronized to an external clock, the power save mode is disabled, and the devices stay in forced PWM mode.

Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads, which maintains high efficiency over a wide load current range.

9.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_J exceeds 145°C typical, the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes high impedance. When T_J decreases by typically 10°C, the converter resumes normal operation.

9.4.1 Soft Start

The TPS6211x has an internal soft-start circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage when a battery or a high-impedance power source is connected to the input of the TPS6211x devices.

The soft start is implemented as a digital circuit increasing the switch current in steps of 300 mA, 600 mA, and 1200 mA for 250 µs each. Then, the switch current limit is set to 2.4 A typical. Therefore, the start-up time depends on the output capacitor and load current. Typical start-up time with a 22-µF output capacitor and 800-mA load current is 1 ms.

The TPS6211x devices can start into a prebiased output. During monotonic prebiased start-up, the N-channel MOSFET is not allowed to turn on until the internal ramp of the device sets an output voltage greater than the prebias voltage.

9.4.2 Constant-Frequency Mode of Operation (Sync = High)

In constant-frequency mode, the output voltage is regulated by varying the duty cycle of the PWM signal in the range of 100% to 10%. Connecting the SYNC pin to a voltage greater than 1.5 V forces the converter to operate permanently in the PWM mode even at light- or no-load currents. The advantage is that the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. The N-MOSFET of the devices stays on even when the current into the output drops to zero. This prevents the device from going into discontinuous mode, and the device transfers unused energy back to the input. Therefore, there is no ringing at the output, which usually occurs in discontinuous mode. The duty cycle range in constant-frequency mode is 100% to 10%.

9.4.3 Power Save Mode of Operation (Sync = Low)

As the load current decreases, the converter enters the power-save mode of operation. During power-save mode, the converter operates with reduced switching frequency in pulse-frequency modulation (PFM), and with a minimum quiescent current to maintain high efficiency. Whenever the average output current goes below the skip threshold, the converter enters the power-save mode. The average current depends on the input voltage. It is about 200 mA at low input voltages and up to 400 mA with maximum input voltage. The average output current must be less than the threshold for at least 32 clock cycles to enter the power-save mode. During the power-save mode, the output voltage is monitored with a comparator, and the output voltage is regulated to a typical value between the nominal output voltage and 0.8% above the nominal output voltage. When the output voltage falls below the nominal output voltage, the P-channel switch turns on. The P-channel switch is turned off as the peak switch current is reached. The N-channel rectifier is turned on, and the inductor current ramps down. As the inductor current approaches zero, the N-channel rectifier is turned off and the switch is turned on starting the next pulse. When the output voltage cannot be reached with a single pulse, the device continues to switch with its normal operating frequency until the comparator detects the output voltage to be 0.8% above the nominal output voltage. This control method reduces the quiescent current to 20 µA (typical), and reduces the switching frequency to a minimum that achieves the highest converter efficiency. Figure 5 shows the typical power save mode operation.

Figure 5. Power Save Mode Output-Voltage Thresholds

Use Equation 1 the typical PFM (SKIP) current threshold for the TPS6211x devices.

Equation 1.

Equation 1 is valid for input voltages up to 7 V. For higher voltages, the skip current threshold is not increased further. The converter enters the fixed-frequency PWM mode as soon as the output voltage falls below V_O – 1.6% (nominal).

9.4.4 100% Duty-Cycle, Low-Dropout Operation

The TPS6211x devices offer the lowest possible input-to-output voltage difference while still maintaining operation with the use of the 100% duty-cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time, taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and is calculated using Equation 2.

Equation 2.

9.4.5 No-Load Operation

When the converter operates in the forced PWM mode and there is no load connected to the output, the converter regulates the output voltage by allowing the inductor current to reverse for a short time.