7.3.1 Soft Start-Up

Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µs. This ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after the COMP voltage ramps, the current limit of the switch is set to half of the normal current limit spec. During this period, the input current is kept below 400 mA (typical). See the start-up waveform of a typical example, Figure 9.

7.3.2 Open LED Protection

Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61161-Q1 monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET and shuts down the IC as soon as the SW voltage exceeds the Vovp threshold and the FB voltage is less than half of regulation voltage for 8 clock cycles. As a result, the output voltage falls to the level of the input supply. The device remains in shutdown mode until it is enabled by toggling the CTRL pin logic. To allow the use of inexpensive low-voltage output capacitor, the TPS61161-Q1 has different open lamp protection thresholds to prevent the internal 40V FET from breaking down. The threshold is set at 38 V. The devices can be selected according to the number of external LEDs and their maximum forward voltage.

7.3.3 Shutdown

The TPS61161-Q1 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During shutdown, the input supply current for the device is less than 1 µA (max). Although the internal FET does not switch in shutdown, there is still a dc current path between the input and the LEDs through the inductor and Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown. However, in the typical application with two or more LEDs, the forward voltage is large enough to reverse bias the Schottky and keep leakage current low.

7.3.4 Undervoltage Lockout

An undervoltage lockout prevents operation of the device at input voltages less than typical 2.2 V. When the input voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned off. If the input voltage rises by undervoltage lockout hysteresis, the IC restarts.

7.3.5 Thermal Shutdown

An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15°C.

7.4.1 LED Brightness Dimming Mode Selection

The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The dimming mode for the TPS61161-Q1 is selected each time the device is enabled. The default dimming mode is PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by the IC every time the IC starts from the shutdown mode.

1. Pull CTRL pin high to enable the TPS61161-Q1, and to start the 1 wire detection window.
2. After the EasyScale detection delay (t_{es_delay}, 100 µs) expires, drive CTRL low for more than the EasyScale detection time (t_{es_detect}, 260 µs).
3. The CTRL pin must be low for more than EasyScale detection time before the EasyScale detection window (t_{es_win}, 1 ms) expires. EasyScale detection window starts from the first CTRL pin low to high transition.

The IC immediately enters the 1-wire mode once these three conditions are met. The EasyScale communication can start before the detection window expires. Once the dimming mode is programmed, it can not be changed without another start-up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5 ms and restarts. See the Dimming Mode Detection and Soft Start (Figure 11) for a graphical explanation.

Figure 11. Dimming Mode Detection and Soft Start PWM Brightness Dimming

7.4.2 PWM Brightness Dimming

When the CTRL pin is constantly high, the FB voltage is regulated to 200 mV typically. However, the CTRL pin allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The relationship between the duty cycle and FB voltage is given by Equation 1.

Equation 1.

where

• Duty = duty cycle of the PWM signal
  200 mV = internal reference voltage

As shown in Figure 12, the IC chops up the internal 200-mV reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED dc current is modulated, which is often referred as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61161-Q1 regulation voltage is independent of the PWM logic voltage level which often has large variations.

For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. The requirement of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the dimming mode selection. Because the CTRL pin is logic only pin, adding external RC filter applied to the pin does not work.

Figure 12. Block Diagram of Programmable FB Voltage Using PWM Signal

7.4.3 Digital 1 Wire Brightness Dimming

The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save the processor power and battery life as it does not require a PWM signal all the time, and the processor can enter idle mode if available.

The TPS61161-Q1 adopts the EasyScale protocol for the digital dimming, which can program the FB voltage to any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo logarithmic curve for the brightness step. See the Table 2 for the FB pin voltage steps. The default step is full scale when the device is first enabled (V_FB = 200 mV). The programmed reference voltage is stored in an internal register. A power reset clears the register value and reset it to default.

7.4.4 EasyScale: 1-Wire Digital Dimming

EasyScale is a simple but flexible one-pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 13 and Table 3 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates from 1.7 kbit/s and up to 160 kbit/s.

Figure 13. EasyScale Protocol Overview

Figure 14. EasyScale™— Bit Coding

All bits are transmitted MSB first and LSB last. Figure 14 shows the protocol without acknowledge request (Bit RFA = 0), Figure 14 with acknowledge (Bit RFA = 1) request. Before both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t_start (2 µs) before the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is needed before the device address byte. The transmission of each byte is closed with an End of Stream condition for at least t_EOS (2 µs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t_LOW and t_HIGH. It can be simplified to:

High Bit: t_HIGH > t_LOW, but with t_HIGH at least 2x t_LOW, see Figure 14.

Low Bit: t_HIGH < t_LOW, but with t_LOW at least 2x t_HIGH, see Figure 14.

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between t_HIGH and t_LOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.

If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time t_ACKN, which is 512 µs maximum then the Acknowledge condition is valid after an internal delay time t_valACK. This means that the internal ACKN-MOSFET is turned on after t_valACK, when the last falling edge of the protocol was detected. The master controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after t_valACK and read back a logic 0. The CTRL pin can be used again after the acknowledge condition ends.

The acknowledge condition may only be requested in case the master device has an open-drain output. For a push-pull output stage, TI recommends using a series resistor in the CRTL line to limit the current to 500 µA for such cases as:

• an accidentally requested acknowledge
• to protect the internal ACKN-MOSFET