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ZHCSKY4B November 2018 – December 2020 TPS55288

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RPM|26
- MPQF533A

散熱焊盤機械數據 (封裝 | 引腳)

RPM|26
- QFND631

訂購信息

6.5 Electrical Characteristics

T_J = -40°C to 125°C, V_IN = 12 V and V_OUT = 20 V. Typical values are at T_J = 25°C, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_IN	Input voltage range		2.7		36	V
V_{VIN_UVLO}	Under voltage lockout threshold	V_IN rising	2.8	2.9	3.0	V
V_{VIN_UVLO}	Under voltage lockout threshold	V_IN falling	2.6	2.65	2.7	V
I_Q	Quiescent current into the VIN pin	IC enabled, no load, no switching. V_IN = 3V to 24V, V_OUT = 0.8V, V_FB = V_REF + 0.1V, R_FSW=100k?, T_J up to 125°C		760	860	μA
I_Q	Quiescent current into the VOUT pin	IC enabled, no load, no switching, V_IN = 2.9V, V_OUT = 3V to 20V, V_FB = V_REF + 0.1V, R_FSW=100k?, T_J up to 125°C		760	860	μA
I_SD	Shutdown current into the VIN pin	IC disabled, V_IN = 2.9V to 14V, T_J up to 125°C		6.8	10	μA
V_CC	Internal regulator output	I_VCC = 50mA, V_IN = 8V, V_OUT = 20V	5.0	5.2	5.4	V
V_{CC_DO}	VCC dropout	V_IN = 5.0V, V_OUT = 20V I_VCC = 60mA		200	320	mV
V_{CC_DO}	VCC dropout	V_IN = 14V, V_OUT = 5.0V, I_VCC = 60mA		110	170	mV
EN/UVLO
V_{EN_H}	EN Logic high threshold	V_CC = 2.7V to 5.5V			1.15	V
V_{EN_L}	EN Logic low threshold	V_CC = 2.7V to 5.5V	0.4			V
V_{EN_HYS}	Enable threshold hysteresis	V_CC = 2.7V to 5.5V	0.05	0.12		V
V_UVLO	UVLO rising threshold at the EN/UVLO pin	V_CC = 3.0V to 5.5V	1.20	1.23	1.26	V
V_{UVLO_HYS}	UVLO threshold hysteresis	V_CC = 3.0V to 5.5V	8	14	20	mV
I_UVLO	Sourcing current at the EN/UVLO pin	V_EN/UVLO = 1.3V	4.5	5	5.5	μA
OUTPUT
V_OUT	Output voltage range		0.8		22	V
V_OVP	Output overvoltage protection threshold		22.5	23.5	24.5	V
V_{OVP_HYS}	Over voltage protection hysteresis			1		V
I_{FB_LKG}	Leakage current at the FB pin	T_J up to 125°C			100	nA
I_{VOUT_LKG}	Leakage current into the VOUT pin	IC disabled, V_OUT = 20V, V_SW2 = 0V, T_J up to 125°C		1	20	μA
I_DISCHG	Output discharge current	V_OUT = 20V, V_CC = 5.2V	40	100	170	mA
INTERNAL REFERENCE DAC
	Resolution of reference voltage DAC			10		bits
INL	Integral non-linearity		–4		4	LSB
DNL	Differential non-linearity		–1		2	LSB
V_{OUT_FULL}	Output voltage when V_REF is set to 1.129V	VOUT_FS=03h, REF=03C0h, V_REF=1.129V	19.7	20	20.3	V
		VOUT_FS=02h, REF=03C0h, V_REF=1.129V	14.78	15	15.22	V
		VOUT_FS=01h, REF=03C0h, V_REF=1.129V	9.85	10	10.15	V
		VOUT_FS=00h, REF=03C0h, V_REF=1.129V	4.93	5	5.07	V
V_{OUT_ZERO}	Output voltage when V_REF is set to 45mV	VOUT_FS=03h, REF=0000h, V_REF=45mV	0.74	0.8	0.86	V
		VOUT_FS=02h, REF=0000h, V_REF=45mV	0.56	0.6	0.64	V
		VOUT_FS=01h, REF=0000h, V_REF=45mV	0.37	0.4	0.43	V
		VOUT_FS=00h, REF=0000h, V_REF=45mV	0.18	0.2	0.22	V
REFERENCE VOLTAGE
V_REF	Reference voltage at the FB/INT pin when using external feedback	External feedback with REF=03C0h	1.117	1.129	1.141	V
		External feedback with REF=02C6h	0.837	0.846	0.855	V
		External feedback with REF=019Ah	0.502	0.508	0.514	V
		External feedback with REF=00D2h	0.276	0.282	0.288	V
POWER SWITCH
R_DS(on)	Low-side MOSFET on resistance on boost side	V_OUT = 20V, V_CC= 5.2V		7.1		mΩ
R_DS(on)	High-side MOSFET on resistance on boost side	V_OUT = 20V, V_CC= 5.2V		7.6		mΩ
INTERNAL CLOCK
f_SW	Switching frequency	R_FSW = 100kΩ	180	200	220	kHz
f_SW	Switching frequency	R_FSW = 9.09kΩ	2000	2200	2400	kHz
t_{OFF_min}	Min. off time	Boost mode		100	145	ns
t_{ON_min}	Min. on time	Buck mode		90	130	ns
V_FSW	Voltage at the FSW pin			1		V
CURRENT LIMIT
I_{LIM_AVG}	Average inductor current limit	R_ILIM = 20kΩ, V_IN = 8V, V_OUT = 20V, f_SW = 400kHz, FPWM	14	16.5	19	A
		R_ILIM = 20kΩ, V_IN = 8V, V_OUT = 20V, f_SW = 400kHz, PFM	14	16.5	19	A
		R_ILIM = 60kΩ, V_IN = 5V, V_OUT = 14V, f_SW = 2.2MHz, FPWM	4	5.5		A
		R_ILIM = 60kΩ, V_IN = 5V, V_OUT = 14V, f_SW = 2.2MHz, PFM	4	5.5		A
I_{LIM_PK}	Peak inductor current limit at high side	R_ILIM = 20k?, V_IN = 8V, V_OUT = 20V, f_SW = 400kHz, FPWM		25		A
I_{LIM_PK}	Peak inductor current limit at high side	R_ILIM = 20k?, V_IN = 8V, V_OUT = 20V, f_SW = 400kHz, PFM		25		A
V_ILIM	Voltage at the ILIM pin	VOUT = 3V		0.6		V
V_SNS	Current loop regulation voltage between the ISP and ISN pins	V_ISN = 2V to 21V,IOUT_LIMIT Register = 11100100b	48	50	52	mV
V_SNS		V_ISN = 2V to 21V,IOUT_LIMIT Register = 10111100b	28	30	32	mV
CABLE VOLTAGE DROOP COMPENSATION
V_CDC	Voltage at the CDC pin	R_CDC = 20k? or floating, V_ISP – V_ISN = 50mV	0.95	1	1.05	V
V_CDC	Voltage at the CDC pin	R_CDC = 20k? or floating, V_ISP – V_ISN = 2mV		40	75	mV
V_{OUT_CDC}	VOUT increase for cable droop compensation	Internal output feedback, CDC[2:0]=111, V_ISP – V_ISN = 50mV	650	700	750	mV
		Internal output feedback, CDC[2:0]=111, V_ISP – V_ISN = 2mV		30	60	mV
		Internal output feedback, CDC[2:0]=001, V_ISP – V_ISN = 50mV	70	100	130	mV
		Internal output feedback, CDC[2:0]=001, V_ISP – V_ISN = 10mV		20	40	mV
I_{FB_CDC}	FB/INT pin sinking current	External output feedback, R_CDC = 20k?, V_ISP – V_ISN = 50mV	7.23	7.5	7.87	μA
		External output feedback, R_CDC = 20k?, V_ISP – V_ISN = 0mV		0	0.3	μA
		External output feedback, R_CDC = floating, V_ISP – V_ISN = 50mV		0	0.3	μA
ERROR AMPLIFIER
I_SINK	COMP pin sink current	V_FB = V_REF + 400mV, V_COMP=1.5V, V_CC=5V		20		μA
I_SOURCE	COMP pin source current	V_FB = V_REF - 400mV, V_COMP=1.5V, V_CC=5V		60		μA
V_CCLPH	High clamp voltage at the COMP pin			1.8		V
V_CCLPL	Low clamp voltage at the COMP pin			0.7		V
G_EA	Error amplifier transconductance			190		μA/V
SOFT START
t_SS	Soft-start time		3	4	5	ms
DR1H GATE DRIVER
V_{DR1H_L}	Low-state voltage drop	V_DR1H – V_SW1, 100-mA sinking		0.1		V
V_{DR1H_H}	High-state voltage drop	V_BOOT1 – V_DR1H, 100-mA sourcing		0.2		V
DR1L GATE DRIVER
V_{DR1L_L}	Low-state voltage drop	100-mA sinking		0.1		V
V_{DR1L_H}	High-state voltage drop	V_CC – V_DR1L, 100-mA sourcing		0.2		V
SPREAD SPECTRUM
I_{DITH_CHG}	Dithering charge current	V_DITH/SYNC = 1.0V, R_FSW=49.9kΩ, voltage rising from 0.85V		2		μA
I_{DITH_DIS}	Dithering discharge current	V_DITH/SYNC = 1.0V, R_FSW=49.9kΩ, voltage falling from 1.15V		2		μA
V_{DITH_H}	Dither high threshold			1.07		V
V_{DITH_L}	Dither low threshold			0.93		V
SYNCHRONOUS CLOCK
V_{SNYC_H}	Sync clock high voltage threshold				1.2	V
V_{SYNC_L}	Sync clock low voltage threshold		0.4			V
t_{SYNC_MIN}	Minimum sync clock pulse width		50			ns
HICCUP
t_HICCUP	Hiccup off time			76		ms
MODE RESISTANCE DETECTION
I_MODE	Sourcing current from the MODE pin	V_MODE = 2.5V	9	10	11	μA
V_{MODE_DT1}	Detection threshold voltage at the MODE pin		1.147	1.220	1.293	V
V_{MODE_DT2}			0.824	0.88	0.936	V
V_{MODE_DT3}			0.571	0.614	0.657	V
V_{MODE_DT4}			0.321	0.351	0.381	V
V_{MODE_DT5}			0.168	0.189	0.210	V
V_{MODE_DT6}			0.080	0.097	0.114	V
V_{MODE_DT7}			0.014	0.027	0.040	V
LOGIC INTERFACE
V_{I2C_IO}	IO voltage range for I²C		1.7		5.5	V
V_{I2C_H}	I²C input high threshold	V_CC = 2.7V to 5.5V			1.2	V
V_{I2C_L}	I²C input low threshold	V_CC = 2.7V to 5.5V	0.4			V
I_{FB/INT_H}	Leakage current into FB/INT pin when outputting high impedance	V_FB/INT = 5V			100	nA
V_{FB/INT_L}	Output low voltage range of the FB/INT pin	Sinking 4mA current		0.03	0.1	V
PROTECTION
T_SD	Thermal shutdown threshold	T_J rising		175		°C
T_{SD_HYS}	Thermal shutdown hysteresis	T_J falling below TSD		20		°C