The device has power-good output that indicates high when the converter output is within the target. The power-good output is an open-drain output and must be pulled up to the VCC pin or an external voltage source (< 5.5 V) through a pullup resistor (typically 30.1 kΩ). The recommended power-good pullup resistor value is 1 kΩ to 100 kΩ.

Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes high when FB reaches threshold equal to V_INTREF – 50 mV. If the FB voltage drops to 80% of the V_INTREF voltage or exceeds 116% of the V_INTREF voltage, the power-good signal latches low after a 2-μs internal delay. The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.

If the input supply fails to power up the device, for example VIN and VCC both stay at zero volts, the PG pin clamps low by itself when this pin is pulled up through an external resistor.

Once VCC voltage level rises above the minimum VCC threshold for valid PGOOD output (maximum 1.5 V), internal power-good circuit is enabled to hold the PGOOD pin to the default status. By default, PGOOD is pulled low and this low-level output voltage is no more than 400 mV with 5.5-mA sinking current. The power-good function is fully activated after the soft-start operation is completed.