ZHCSDR8 May 2015 TPS544B25 , TPS544C25
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Linear Regulators BP3 and BP6
- 8.3.2 Input Undervoltage Lockout (UVLO)
- 8.3.3 Turn-On and Turn-Off Delay and Sequencing
- 8.3.4 Voltage Reference
- 8.3.5 Differential Remote Sense
- 8.3.6 Set Output Voltage and Adapative Voltage Scaling (AVS)
- 8.3.7 Reset VOUT
- 8.3.8 Switching Frequency and Synchronization
- 8.3.9 Soft-Start and TON_RISE Command
- 8.3.10 Pre-Biased Output Start-Up
- 8.3.11 Soft-Stop and TOFF_FALL Command
- 8.3.12 Current Monitoring and Low-Side MOSFET Overcurrent Protection
- 8.3.13 High-Side MOSFET Short-Circuit Protection
- 8.3.14 Over-Temperature Protection
- 8.3.15 Output Overvoltage and Undervoltage Protection
- 8.3.16 TON_MAX Fault
- 8.3.17 Power Good (PGOOD) Indicator
- 8.3.18 Fault Protection Responses
- 8.3.19 Switching Node
- 8.3.20 PMBus General Description
- 8.3.21 PMBus Address
- 8.3.22 PMBus Connections
- 8.3.23 Auto ARA (Alert Response Address) Response
- 8.4 Device Functional Modes
- 8.5 Supported PMBus Commands
- 8.6
Register Maps
- 8.6.1 OPERATION (01h)
- 8.6.2 ON_OFF_CONFIG (02h)
- 8.6.3 CLEAR_FAULTS (03h)
- 8.6.4 WRITE_PROTECT (10h)
- 8.6.5 STORE_DEFAULT_ALL (11h)
- 8.6.6 RESTORE_DEFAULT_ALL (12h)
- 8.6.7 CAPABILITY (19h)
- 8.6.8 SMBALERT_MASK (1Bh)
- 8.6.9 VOUT_MODE (20h)
- 8.6.10 VOUT_COMMAND (21h)
- 8.6.11 VOUT_MAX (24h)
- 8.6.12 VOUT_TRANSITION_RATE (27h)
- 8.6.13 VOUT_SCALE_LOOP (29h)
- 8.6.14 VIN_ON (35h)
- 8.6.15 VIN_OFF (36h)
- 8.6.16 IOUT_CAL_OFFSET (39h)
- 8.6.17 VOUT_OV_FAULT_LIMIT (40h)
- 8.6.18 VOUT_OV_FAULT_RESPONSE (41h)
- 8.6.19 VOUT_OV_WARN_LIMIT (42h)
- 8.6.20 VOUT_UV_WARN_LIMIT (43h)
- 8.6.21 VOUT_UV_FAULT_LIMIT (44h)
- 8.6.22 VOUT_UV_FAULT_RESPONSE (45h)
- 8.6.23 IOUT_OC_FAULT_LIMIT (46h)
- 8.6.24 IOUT_OC_FAULT_RESPONSE (47h)
- 8.6.25 IOUT_OC_WARN_LIMIT (4Ah)
- 8.6.26 OT_FAULT_LIMIT (4Fh)
- 8.6.27 OT_FAULT_RESPONSE (50h)
- 8.6.28 OT_WARN_LIMIT (51h)
- 8.6.29 TON_DELAY (60h)
- 8.6.30 TON_RISE (61h)
- 8.6.31 TON_MAX_FAULT_LIMIT (62h)
- 8.6.32 TON_MAX_FAULT_RESPONSE (63h)
- 8.6.33 TOFF_DELAY (64h)
- 8.6.34 TOFF_FALL (65h)
- 8.6.35 STATUS_BYTE (78h)
- 8.6.36 STATUS_WORD (79h)
- 8.6.37 STATUS_VOUT (7Ah)
- 8.6.38 STATUS_IOUT (7Bh)
- 8.6.39 STATUS_INPUT (7Ch)
- 8.6.40 STATUS_TEMPERATURE (7Dh)
- 8.6.41 STATUS_CML (7Eh)
- 8.6.42 STATUS_MFR_SPECIFIC (80h)
- 8.6.43 READ_VOUT (8Bh)
- 8.6.44 READ_IOUT (8Ch)
- 8.6.45 READ_TEMPERATURE_2 (8Eh)
- 8.6.46 PMBUS_REVISION (98h)
- 8.6.47 MFR_VOUT_MIN (A4h)
- 8.6.48 IC_DEVICE_ID (ADh)
- 8.6.49 IC_DEVICE_REV (AEh)
- 8.6.50 MFR_SPECIFIC_00 (D0h)
- 8.6.51 OPTIONS (MFR_SPECIFIC_21) (E5h)
- 8.6.52 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
-
9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1 TPS544C25 4.5-V to 18-V Input, 0.95-V Output, 30-A Converter
- 9.2.2 Design Requirements
- 9.2.3
Design Procedure
- 9.2.3.1 Switching Frequency Selection
- 9.2.3.2 Inductor Selection
- 9.2.3.3 Output Capacitor Selection
- 9.2.3.4 Input Capacitor Selection
- 9.2.3.5 Bootstrap Capacitor Selection
- 9.2.3.6 BP6 and BP3
- 9.2.3.7 R-C Snubber and VIN Pin High-Frequency Bypass
- 9.2.3.8 Temperature Sensor
- 9.2.3.9 Key PMBus Parameter Selection
- 9.2.3.10 Output Voltage Setting and Frequency Compensation Selection
- 9.2.4 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
RVF Package
40-Pin LQFN
(Top View)
Pin Functions
| NAME | NO. | DESCRIPTION |
|---|---|---|
| ADDR0 | 3 | Sets low-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND. |
| ADDR1 | 2 | Sets high-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND. |
| AGND | 38 | Analog ground return for controller device. Connect to GND at the thermal tab. |
| BP3 | 27 | Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a minimum of 2.2 µF to AGND. BP3 is not designed to power external circuit. |
| BP6 | 28 | Output of the 6.5-V on-board regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 2.2 µF to GND. TI recommends using an additional 100-nF typical bypass capacitor for reduce ripple on BP6. |
| BOOT | 7 | Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the SW pin. |
| CLK | 5 | PMBus CLK pin. See Supported PMBus Commands section. |
| CNTL | 1 | PMBus CNTL pin. See Supported PMBus Commands section. The CNTL pin has an internal pull-up and floats high when left floating. |
| COMP | 35 | Output of the error amplifier. Connect compensator network from this pin to the FB pin. |
| DATA | 4 | PMBus DATA pin. See Supported PMBus Commands section. |
| DIFFO | 33 | Output of the differential remote sense amplifier. |
| FB | 34 | Feedback pin for the control loop. Negative input of the error amplifier. |
| GND | 13 | Power stage ground return. |
| 14 | ||
| 15 | ||
| 16 | ||
| 17 | ||
| 18 | ||
| 19 | ||
| 20 | ||
| PGND | 26 | Power ground return for controller device. Connect to GND at the thermal tab. |
| PGOOD | 36 | Power good output. Open drain output that floats up when the device is operating and in regulation. Any fault condition causes this pin to pull low. Please refer to Table 6 for the possible sources to pull down PGOOD pin. |
| RT | 40 | Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency. Do not leave this pin floating. |
| SMBALERT | 6 | SMBus alert pin. See SMBus specification. |
| SW | 8 | Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this group of pins. |
| 9 | ||
| 10 | ||
| 11 | ||
| 12 | ||
| SYNC/RESET_B | 39 | For switching frequency synchronization or output voltage reset. The SYNC function allows synchronizing the oscillator to an external source that is either slower of faster than the nominal free running oscillator frequency. To use the SYNC function, VSET pin should be pulled up to BP3 or set the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) if VSET function is used; if synchronization is not required, pull the SYNC pin to BP3. If the VSET pin is connected to AGND through a valid resistor to configure default output voltage, SYNC/RESET_B is configured as RESET_B function when FORCE_SYNC is not set. Then the logic low on the SYNC/RESET_B pin restores the output voltage to default value set by VSET without power cycling. When SYNC/RESET_B is configured as RESET_B function, there is an internal 200kΩ pull-up resistor to BP3. |
| TSNS/SS | 37 | External temperature sense signal input or alternatively used to set default soft-start time by connecting a resistor from this pin to AGND. Do not leave this pin floating. Disable TSNS by pulling TSNS to AGND and unsetting SS_DET_DIS in OPTIONS (MFR_SPECIFIC_21) (E5h) in applications where neither is needed. |
| VDD | 29 | Input power to the controller. Connect a low impedance bypass with a minimum of 1 µF to AGND. The VDD voltage is also used for input feed-forward. VIN and VDD must be the same potential for accurate short circuit protection. |
| VIN | 21 | Input power to the power stage. Low impedance bypassing of these pins to GND is critical. |
| 22 | ||
| 23 | ||
| 24 | ||
| 25 | ||
| VOUTS+ | 31 | Load voltage sensing, positive side. This sensing provides remote sensing for the PMBus interface reporting and the voltage control loop. |
| VOUTS– | 32 | Load voltage sensing, negative or common side. This sensing provides remote sensing for the PMBus interface reporting and the voltage control loop. |
| VSET | 30 | Optionally configures default output voltage setting by connecting a resistor from this pin to AGND. See Set Default Output Voltage by VSET for details. If VSET is not used, pull this pin up to BP3. Do not leave this pin floating. |
| Thermal tab | Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper operation. | |