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ZHCSDR8 May 2015 TPS544B25 , TPS544C25

PRODUCTION DATA.

封裝選項

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. Figure 55 shows the recommended PCB layout configuration. A list of PCB layout considerations using these devices are listed below.

As with any switching regulator, there are several signal paths that conduct fast switching voltages or currents. Minimize the loop area formed by these paths and their bypass connections.
Bypass the VIN pins to GND with a low-impedance path. Power-stage input bypass capacitors should be as close as physically possible to the VIN and GND pins. Additionally, a high-frequency bypass capacitor in 0402 package on the VIN pins can help to reduce switching spikes, which can be tucked right underneath the IC on the other side of the PCB to keep a minimum loop.
BP6 bypass capacitor carries large switching current for gate driver. Bypassing the BP6 pin to GND with a low-impedance path is very critical to the stable operation of the TPS544x25 devices. Place BP6 high-frequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground.
The VDD and BP3 also require good local bypassing. Place bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground and this return loop should be kept away from fast switching voltage and main current path, as well as BP6 current path. Poor bypassing on VDD and BP3 can degrade the performance of the regulator.
Keep signal components local to the device, and place them as close as possible to the pins to which they are connected. These components include the feedback resistors, the RT resistor, the VSET resistor, the SS resistor, as well as ADDR0 and ADDR1 resistors. These components should also be kept away from fast switching voltage and current paths. Those components can be terminated to GND with minimum return loop or bypassed to a separate low impedance analog ground (AGND) copper area, which is isolated from fast switching voltage and current paths and has single connection to PGND on the thermal tab via AGND pin. See Figure 55 for placement recommendation.
The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low-noise, low-impedance path to ensure accurate current monitoring.
Minimize the SW copper area for best noise performance. Route sensitive traces away from SW and BOOT, as these nets contain fast switching voltages, and lend easily to capacitive coupling.
Snubber component placement is critical to its effectiveness of ringing reduction. These components should be on the same layer as the TPS544x25 devices, and be kept as close as possible to the SW and GND copper areas.
The VIN and VDD pins must be the same potential for accurate short circuit protection, but high frequency switching noise on the VDD pin can degrade performance. VDD should be connected to VIN through a trace from the input copper area. Optionally form a small low-pass R-C between VIN and VDD, with the VDD bypass capacitor (1 µF) and a 0-2 Ω resistor between VIN and VDD. See Figure 55.
Route the VOUTS+ and VOUTS– lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. It is critical that these traces be kept away from switching or noisy areas which can add differential-mode noise.
Routing of the temperature sensor traces is critical to the noise performance of temperature monitoring. Keep these traces away from switching areas or high current paths on the layout. It is also recommended to use a small 1-nF capacitor from TSNS/SS to AGND to improve the noise performance of temperature readings.

11.2 Layout Example

(A) Connect to AGND with setting resistor or pull up to BP3 if not used.
(B) Bypass for internal regulators BP3, BP6, VDD. Use multiple vias to reduce parasitic inductance
(C) Place VIN bypass capacitors as close as possible to device, with best high frequency capacitor closest to VIN and GND pins
(D) Kelvin connect to TPS544C25 VOUTS– and VOUTS+ pins
(E) Sense point should be directly at the load
(F) For best efficiency, use a heavy weight copper and place these planes on multiple PCB layers
(G) Minimize SW area for least noise. Keep sensitive traces away from SW and BOOT on all layers
(H) AGND and PGND are only connected together on Thermal Pad.
(I) Optional SYNC/RESET_B Signal. Pull up to BP3 if not used.
(J) Pull up to BP6 or external voltage to use PGOOD.
(K) Maintain feedback and compensation network components localized to the device.
(L) Internal AGND Plane to reduce the BP3 and VDD bypass parasitics.
(M) Connect AGND to Thermal Pad
(N) Connect PGND to Thermal Pad

Figure 55. PCB Layout Recommendation

11.2.1 Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 56 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.

TPS544C25 TPS544B25 mech_thermal_profile_slusc81.gif

Figure 56. Recommended Reflow Oven Thermal Profile

Table 18. Recommended Thermal Profile Parameters

PARAMETER		MIN	TYP	MAX	UNIT
RAMP UP AND RAMP DOWN
r_RAMP(up)	Average ramp-up rate, T_S(max) to T_P			3	°C/s
r_RAMP(down)	Average ramp-down rate, T_P to T_S(max)			6	°C/s
PRE-HEAT
T_S	Pre-heat temperature	150		200	°C
t_S	Pre-heat time, T_S(min) to T_S(max)	60		180	s
REFLOW
T_L	Liquidus temperature		217		°C
T_P	Peak temperature			260	°C
t_L	Time maintained above liquidus temperature, T_L	60		150	s
t_P	Time maintained within 5 °C of peak temperature, T_P	20		40	s
t_25P	Total time from 25 °C to peak temperature, T_P			480	s

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訂購信息

11 Layout

11.1 Layout Guidelines

11.2 Layout Example

11.2.1 Mounting and Thermal Profile Recommendation

Table 18. Recommended Thermal Profile Parameters