ZHCSM62C September 2020 – December 2021 TPS542A50
PRODUCTION DATA
Table 7-11 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-11 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | ID | Go | |
| 0x1 | STATUS | Go | |
| 0x2 | VOUT_ADJ1 | Go | |
| 0x3 | VOUT_ADJ2 | Go | |
| 0x4 | CONFIG1 | Go | |
| 0x5 | CONFIG2 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-12 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |