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ZHCSFG9A August 2016 – August 2016 TPS54116-Q1

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTW|24

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Voltage Range	PVIN, AVIN, ENSW, ENLDO, PGOOD	-0.3	7	V
	FB, COMP, SS/TRK, ILIM	-0.3	3	V
	RT/SYNC	-0.3	6	V
	BOOT with respect to SW	-0.3	7	V
	LDOIN, VTTSNS, VDDQSNS	-0.3	3.6	V
	SW	-0.6	7	V
	SW, 10-ns transient	-4	10	V
	VTT, VTTREF	-0.3	3.6	V
Current Range	RT/SYNC	-100	100	µA
Current Range	PGOOD	-5	5	mA
Operating junction temperature		-40	150	°C
Storage temperature, T_stg		-65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_(AVIN), V_(PVIN)	Input voltage	2.95	6	V
V_OUT	Buck output voltage	0.6	4.5	V
I_OUT	Buck output current	0	4	A
V_(VDDQSNS)	VDDQSNS input voltage	1	3.5	V
V_(LDOIN)	LDOIN input voltage	VTT + VDO	3.5	V
V_(VTT), V_(VTTREF)	VTT and VTTREF output voltage	0.5	3.5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54116-Q1	UNIT
		RTW (WQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	36.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	35.0
R_θJB	Junction-to-board thermal resistance	14.3
ψ_JT	Junction-to-top characterization parameter	0.4
ψ_JB	Junction-to-board characterization parameter	14.4
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (AVIN and PVIN PINS)
	AVIN and PVIN operating		2.95		6	V
	AVIN internal UVLO threshold	AVIN rising		2.7	2.8	V
	AVIN internal UVLO hysteresis			0.05	0.12	V
	Iq shutdown	V_(ENSW) = V_(ENLDO) = 0 V, V_(VDDQSNS) = 1.8 V, TJ = 25°C		1	3.5	µA
	Iq operating — LDO and buck enabled	V_(ENSW) = V_(ENLDO) = V_(AVIN) = 5 V, V_(FB) = 0.7 V, V_(VDDQSNS) = 1.8 V, TJ = 25°C		650	800	µA
	Iq operating — LDO enabled, buck disabled	V_(ENLDO) = V_(AVIN) = 5 V, V_(ENSW) = 0 V, V_(VDDQSNS) = 1.8 V, TJ = 25°C		190	300	µA
	Iq operating — LDO disabled, buck enabled	V_(ENSW) = V_(AVIN) = 5 V, V_(ENLDO) = 0 V, V_(FB) = 0.7 V, V_(VDDQSNS) = 1.8 V, TJ = 25°C		570	700	µA
ENABLE (ENSW and ENLDO PINS)
V_ENRISING	ENLDO rising threshold	ENLDO voltage ramping up		1.20		V
V_ENFALLING	ENLDO falling threshold	ENLDO voltage ramping down		1.17		V
	ENLDO input current above voltage threshold	V_(ENLDO) = Enable threshold + 50 mV		-4.4		µA
I_p	ENLDO input current below voltage threshold	V_(ENLDO) = Enable threshold - 50 mV		-1.7
I_h	ENLDO hysteresis current			-2.7
V_ENRISING	ENSW rising threshold	ENSW voltage ramping up		1.20		V
V_ENFALLING	ENSW falling threshold	ENSW voltage ramping down		1.17		V
	ENSW input current above voltage threshold	V_(ENSW) = Enable threshold + 50 mV		-4.4		µA
I_p	ENSW input current below voltage threshold	V_(ENSW) = Enable threshold - 50 mV		-1.7
I_h	ENSW hysteresis current			-2.7
	Input current above voltage threshold with ENLDO and ENSW connected	V_(ENLDO) = V_(ENSW) = Enable threshold + 50 mV		-8.5		µA
	Input current below voltage threshold with ENLDO and ENSW connected	V_(ENLDO) = V_(ENSW) = Enable threshold - 50 mV		-3.4		µA
	Hysteresis current with ENLDO and ENSW connected			-5.1		µA
VOLTAGE REFERENCE AND ERROR AMPLIFIER (FB AND COMP PINS)
V_REF	Voltage Reference		0.594	0.6	0.606	V
	FB pin input current			7		nA
gm_EA	Error Amp transconductance (gm)	-2 µA < I_(COMP) < 2 µA, V_(COMP) = 1 V		260	360	µS
	Error Amp source/sink	V_(COMP) = 1 V, V_(FB) = 100 mV overdrive		22		µA
MOSFETS AND POWER STAGE (SW AND BOOT PINS)
	High side switch resistance	V_(BOOT-SW) = 5 V		33	66	mΩ
	High side switch resistance	V_(BOOT-SW) = 3.3 V		42	84	mΩ
	Low side switch resistance	V_(PVIN) = 5 V		25	50	mΩ
	Low side switch resistance	V_(PVIN) = 3.3 V		30	60	mΩ
	BOOT-SW UVLO	V_(PVIN) = 2.95 V		2.2		V
	High-side FET current limit	V_(PVIN) = 6V, R_(ILIM) = 100k	5.2	6.6	8.2	A
	High-side FET current limit	V_(PVIN) = 6V, R_(ILIM) = 200k	1.5	3	3.8	A
	Low-side FET reverse current limit		2	4.5		A
gm_PS	V_(COMP) to I_(SW)peak transconductance	R_(ILIM) = 100k		16		A/V
	Minimum pulse width	Measured at 50% points on V_(SW), I_OUT = 2 A		60		ns
	Minimum pulse width	Measured at 50% points V_(SW), V_(PVIN) = 5 V, I_OUT = 0 A, TJ = -40°C to 125°C		100	125	ns
	Minimum off-time	Prior to skipping off pulses, I_OUT = 2 A		60		ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/SYNC PIN)
	Switching frequency range using RT mode		100		2500	kHz
	Switching frequency	R_(RT/SYNC) = 150 kΩ	370	400	430	kHz
		R_(RT/SYNC) = 27 kΩ	1910	2070	2230	kHz
		V_(RT/SYNC) > 2.2 V or V_(RT/SYNC) < 0.35 V	340	420	480	kHz
	Switching frequency range using SYNC mode		100		2500	kHz
	Minimum SYNC input pulse width		10			ns
	RT/SYNC high threshold			1.5	2.2	V
	RT/SYNC low threshold		0.35	0.4		V
	RT/SYNC rising edge to SW rising edge delay	f_SW = 500 kHz	30	45	80	ns
	RT to SYNC lock in time	R_(RT/SYNC) = 150 kΩ		55		µs
	SYNC to RT lock in time			60		µs
	Internal RT to SYNC lock in time	Logic high or logic low at RT/SYNC to SYNC signal		55		µs
	SYNC to internal RT lock in time	SYNC signal to logic high or logic low at RT/SYNC		60		µs
SOFT START AND TRACKING (SS/TRK PIN)
V_SSTHR	SS voltage threshold			0.15		V
I_SS	Charge Current	V_(SS/TRK) < V_SSTHR		47		µA
I_SS	Charge Current	V_(SS/TRK) > V_SSTHR	1.5	2.4	3.2	µA
	SS/TRK to FB matching	V_(SS/TRK) = 0.3 V		60		mV
	SS/TRK to reference crossover	98% normal		0.85	1	V
	SS/TRK discharge voltage (overload)	V_(FB) = 0 V		120		mV
	SS/TRK discharge voltage (fault)	V_(FB) = 0 V		5		mV
	SS/TRK discharge current (overload)	V_(FB) = 0 V, V_(SS/TRK) = 0.4 V		160		µA
	SS/TRK discharge current (AVIN UVLO, ENSW low, thermal fault)	V_(AVIN) = 5 V, V_(SS/TRK) = 0.4 V		760		µA
POWER GOOD (PGOOD PIN)
	Threshold	V_(FB) falling (fault)		91	95	% V_REF
		V_(FB) rising (good)		94
		V_(FB) rising (fault)	105	109
		V_(FB) falling (good)		106
	Hysteresis	V_(FB) falling and rising		3
	Output high leakage	V_(FB) = V_REF, V_(PGOOD) = 5.5 V		5	125	nA
	On resistance	V_(AVIN) = 2.95 V		85	170	Ω
	Minimum V_(AVIN) for valid output	V_(PGOOD) < 0.5 V, I_(PGOOD) = 100 µA		1.3	1.7	V
TERMINATION REGULATOR INPUTS (VLDOIN AND VDDQSNS PINS)
	V_(LDOIN) Operating				3.5	V
V_DO	DC V_(LDOIN) – V_(VTT) dropout	1.2 V < V_(VDDQSNS) < 2.5 V, I_(VTT) = 0.5 A, V_(VTT) = V_(VTTREF) - 40 mV			0.15	V
V_DO	DC V_(LDOIN) – V_(VTT) dropout	1.2 V < V_(VDDQSNS) < 2.5 V, I_(VTT) = 1.5 A, V_(VTT) = V_(VTTREF) - 40 mV			0.45	V
	VLDOIN supply current	V_(LDOIN) = 1.8 V, TJ = 25°C			1	µA
	VDDQSNS input current	V_(VDDQSNS) = 1.8 V		39	46	µA
VTTREF OUTPUT (VTTREF PIN)
V_(VTTREF)	VTTREF output voltage			V_(VDDQSNS)/2		V
V_(VTTREF)TOL	VTTREF output voltage difference from V_(VDDQSNS)/2	\|I_(VTTREF)\| < 10 mA, V_(VDDQSNS) = 1.8 V	-18		18	mV
		\|I_(VTTREF)\| < 10 mA, V_(VDDQSNS) = 1.5 V	-15		15
		\|I_(VTTREF)\| < 10 mA, V_(VDDQSNS) = 1.2 V	-15		15
		\|I_(VTTREF)\| < 5 mA, V_(VDDQSNS) = 1.2 V	-12		12
I_(VTTREF)SRC	VTTREF source current limit	V_(VDDQSNS) = 1.8 V, V_(VTTREF) = 0 V	10	18		mA
I_(VTTREF)SNK	VTTREF sink current limit	V_(VDDQSNS) = 0 V, V_(VTTREF) = 1.8 V	10	19		mA
I_(VTTREF)DIS	VTTREF discharge current	TJ = 25°C, V_(VTTREF) = 0.5V, V_(ENLDO) = 0 V	0.9	1.1		mA
VTT OUTPUT (VTT PIN)
V_(VTT)	VTT output voltage			V_(VTTREF)		V
V_(VTT)TOL	VTT output voltage tolerance to VTTREF	\|I_(VTT)\|≤ 10 mA, 1.2 V ≤ V_(VDDQSNS) ≤ 1.8 V	-20		20	mV
		\|I_(VTT)\|≤ 1 A, 1.2 V ≤ V_(VDDQSNS) ≤ 1.8 V	-30		30
		\|I_(VTT)\|≤ 1.5 A, 1.2 V ≤ V_(VDDQSNS) ≤ 1.8 V	-40		40
I_(VTT)SRC	VTT source current limit	V_(VDDQSNS) = 1.8 V, V_(VTT) = V_(VTTSNS) = 0.7 V	1.5	2.5		A
I_(VTT)SNK	VTT sink current limit	V_(VDDQSNS) = 1.8 V, V_(VTT) = V_(VTTSNS) = 1.1 V	1.5	2.5		A
I_(VTTSNS)BIAS	VTTSNS input bias current		-0.1		0.1	µA
I_(VTT)DIS	VTT discharge current	TJ = 25°C, V_(VTT) = 0.5 V, V_(ENLDO) = 0 V	4.8	6		mA
THERMAL SHUTDOWN
	Thermal shutdown temperature			175		℃
	Thermal shutdown hysteresis			16		℃

6.6 Typical Characteristics

Figure 1. Shutdown Supply Current vs Temperature

Figure 3. Non-switching Supply Current - LDO Enabled and Buck Disabled vs Temperature

Figure 5. ENSW and ENLDO Voltage Threshold vs Temperature

Figure 7. ENSW and ENLDO Parallel Input Current vs Temperature

Figure 9. Error Amplifier Transconductance vs Temperature

V_(PVIN) = 5 V

Figure 11. High-side Current Limit vs Temperature

Figure 13. V_(COMP) to I_(SW) Transconductance vs Temperature

T_A = 25°C

Figure 15. Minimum pulse-width vs Load Current

T_A = 25°C

Figure 17. Switching Frequency vs R_(RT/SYNC)High Range

R_(RT/SYNC) = 27 kΩ

Figure 19. Switching Frequency vs Temperature

V_(SS/TRK) < V_SS(THR)

Figure 21. I_(SS/TRK) vs Temperature

T_A = 25°C

Figure 23. V_(FB) vs V_(SS/TRK)

VDDQSNS = 1.8 V

V_IN = 5 V

Figure 25. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

VDDQSNS = 1.35 V

V_IN = 5 V

Figure 27. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

VDDQSNS = 1.8 V

V_IN = 5 V

Figure 29. VTT Regulation to VTTREF vs I_(VTT)

VDDQSNS = 1.35 V

V_IN = 5 V

Figure 31. VTT Regulation to VTTREF vs I_(VTT)

VDDQSNS = 1.5 V

V_IN = 5 V

Figure 33. VTT Dropout

V_(VTT) = 1.5 V	V_IN = 5 V	I_(VTT) = –1 A
T_A = 25°C

Figure 35. VTT Sinking Frequency Response

f_SYNC = 2.1 MHz	V_IN = 5 V	L = 744373240068
T_A = 25°C

Figure 37. Efficiency

f_SYNC = 400 kHz	V_IN = 5 V	L = 744310200
T_A = 25°C

Figure 39. Efficiency

Figure 2. Non-switching Supply Current - LDO and Buck Enabled vs Temperature

Figure 4. Non-switching Supply Current - LDO Disabled and Buck Enabled vs Temperature

Figure 6. ENSW and ENLDO Individual Input Current vs Temperature

Figure 8. Voltage Reference vs Temperature

Figure 10. MOSFET R_ds(on) vs Temperature

V_(PVIN) = 5 V

T_A = 25°C

Figure 12. High-side Current Limit vs R_ILIM

Figure 14. Minimum Pulse-width vs Temperature

T_A = 25°C

Figure 16. Switching Frequency vs R_(RT/SYNC)Low Range

R_(RT/SYNC) = 150 kΩ

Figure 18. Switching Frequency vs Temperature

Internal RT

Figure 20. Switching Frequency vs Temperature

V_(SS/TRK) > V_SS(THR)

Figure 22. I_(SS/TRK) vs Temperature

Figure 24. PGOOD Thresholds vs Temperature

VDDQSNS = 1.5 V

V_IN= 5 V

Figure 26. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

VDDQSNS = 1.2 V

V_IN= 5 V

Figure 28. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

VDDQSNS = 1.5 V

V_IN = 5 V

Figure 30. VTT Regulation to VTTREF vs I_(VTT)

VDDQSNS = 1.2 V

V_IN = 5 V

Figure 32. VTT Regulation to VTTREF vs I_(VTT)

V_(VTT) = 1.5 V	V_IN = 5 V	I_(VTT) = +1 A
T_A = 25°C

Figure 34. VTT Sourcing Frequency Response

f_SYNC = 2.1 MHz	V_IN = 3.3 V	L = 744373240068
T_A = 25°C

Figure 36. Efficiency

f_SYNC = 400 kHz	V_IN = 3.3 V	L = 744310200
T_A = 25°C

Figure 38. Efficiency