ZHCSBM9C SEPTEMBER 2013 – June 2018 TPS53513
PRODUCTION DATA.
The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin.
When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-up sequence. The controller then uses the first 400 μs to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. During this period, the MODE pin also senses the resistance attached to this pin to determine the operation mode. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. the ramping up time is 1 ms. The device maintains smooth and constant ramp-up of the output voltage during start-up regardless of load current.