ZHCSBM9C SEPTEMBER 2013 – June 2018 TPS53513
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 5-V LDO and VREG Start-Up
- 7.3.2 Enable, Soft Start, and Mode Selection
- 7.3.3 Frequency Selection
- 7.3.4 D-CAP3 Control and Mode Selection
- 7.3.5 Power-Good
- 7.3.6 Current Sense and Overcurrent Protection
- 7.3.7 Overvoltage and Undervoltage Protection
- 7.3.8 Out-Of-Bounds Operation
- 7.3.9 UVLO Protection
- 7.3.10 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.1 5-V LDO and VREG Start-Up
The TPS53513 device has an internal 5-V LDO feature using input from VDD and output to VREG. When the VDD voltage rises above 2.8 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry. The VREG voltage also provides the supply voltage for the gate drives.
Figure 33. Power-up Sequence Waveforms