7.1 Overview

The TPS53219A is a high-efficiency, single-channel, synchronous buck regulator controller suitable for low output voltage point-of-load applications in computing and similar digital consumer applications. The device features proprietary D-CAP mode control combined with an adaptive ON-time architecture. This combination is ideal for building modern low duty ratio, ultra-fast load step response DC–DC converters. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 3 V up to 28 V. The D-CAP mode uses the ESR of the output capacitors to sense the device current. One advantage of this control scheme is that it does not require an external phase compensation network. This allows a simple design with a low external component count. Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive ON-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step-up of the load.

The TPS53219A has a MODE pin to select between auto-skip mode and forced continuous conduction mode (FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to 5.6 ms as shown in Table 1. The strong gate drivers allow low R_DS(on) FETs for high-current applications.

When the device starts (either by EN or VDD UVLO), the TPS53219A sends out a current that detects the resistance connected to the MODE pin to determine the soft-start time. After that (and before V_OUT start to ramp up) the MODE pin becomes a high-impedance input to determine skip mode or FCCM mode operation. When the voltage on the MODE pin is higher than 1.3 V, the converter enters into FCCM mode. If the voltage on MODE pin is less than 1.3 V, then the converter operates in skip mode.

TI recommends to connect the MODE pin to the PGOOD pin if FCCM mode is desired. In this configuration, the MODE pin is connected to the GND potential through a resistor when the device is detecting the soft-start time thus correct soft-start time is used. The device starts up in skip mode and only after the PGOOD pin goes high does the device enter into FCCM mode. When the PGOOD pin goes high there is a transition between skip mode and FCCM. A minimum off-time of 60 ns on DRVL is provided to avoid a voltage spike on the DRVL pin caused by parasitic inductance of the driver loop and gate capacitance of the low-side MOSFET.

For proper operation, the MODE pin must not be connected directly to a voltage source.