ZHCSH96H MARCH 2007 – May 2019 TPS40192 , TPS40193
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Inductor Selection
- 8.2.2.3 Output Capacitor Selection (C8)
- 8.2.2.4 Peak Current Rating of the Inductor
- 8.2.2.5 Input Capacitor Selection (C7)
- 8.2.2.6 MOSFET Switch Selection (Q1, Q2)
- 8.2.2.7 Boot Strap Capacitor
- 8.2.2.8 Input Bypass Capacitor (C6)
- 8.2.2.9 BP5 Bypass Capacitor (C5)
- 8.2.2.10 Input Voltage Filter Resistor (R11)
- 8.2.2.11 Short Circuit Protection (R9)
- 8.2.2.12 Feedback Compensation (Modeling the Power Stage)
- 8.2.2.13 Feedback Divider (R7, R8)
- 8.2.2.14 Error Amplifier Compensation (R6, R10, C1, C2, C3)
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購(gòu)信息
8.2.2.12 Feedback Compensation (Modeling the Power Stage)
The DC gain of the modulator is given by Equation 26.
Because the peak-to-peak ramp voltage given in the Electrical Characteristics table is projected from the ramp slope over a full switching period, the modulator gain can be calculated as Equation 27. The maximum modulator gain for this design is found to be 14 (23 dB).
The L-C filter applies a double pole at the resonance frequency described in Equation 28.
At any frequency lower than this ( 11.3 kHz), the power stage has a DC gain of 23 dB and at any higher frequency the power stage gain drops off at -40 dB per decade. The ESR zero is approximated in Equation 29.
Using two 100 µF, 2.5 mΩ ESR ceramic output capacitors, the calculated fESR of 636 kHz is greater than 1/5th the switching frequency, and therefore outside the scope of the error amplifier design. The gain of the power stage would change to –20 dB per decade above fESR. The straight line approximation the power stage gain is described in Figure 16.
The following compensation design procedure assumes fESR > fRES. For designs using large high-ESR bulk capacitors on the output where fESR < fRES. Type-II compensation can be used but is not described in this data sheet.
Figure 16. Approximation of Power Stage Gain 