ZHCS155C March 2011 – November 2023 TPS40170
PRODUCTION DATA
Top Copper, Viewed From Top illustrates an example layout. For the controller, it is important to carefully connect noise sensitive signals such as RT, SS, FB, and comp as close to the IC as possible and connect to AGND as shown. The PowerPad must be connected to any internal PCB ground planes using multiple vias directly under the IC. The AGND and PGND must be connected at a single point.
When using high-performance FETs such as NexFET? from Texas Instruments, careful attention to the layout is required. Minimize the distance between positive node of the input ceramic capacitor and the drain pin of the control (high-side) FET. Minimize the distance between the negative node of the input ceramic capacitor and the source pin of the synchronization (low-side) FET. Because of the large gate drive, smaller gate charge, and faster turn-on times of the high-performance FETs, it is recommended to use a minimum of 4, 10 μF ceramic input capacitors such as TDK #C3216X5R1A106M. Ensure the layout allows a continuous flow of the power planes.
The layout of the HPA578 EVM is shown in Top Copper, Viewed From Top through Internal Layer 2, Viewed from Top for reference.