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SLUS660I September 2005 – January 2015 TPS40140

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHH|36
- MPQF144E

散熱焊盤機械數據 (封裝 | 引腳)

RHH|36
- QFND054L

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage	VDD, UVLO ≤ VDD, RT, SS	–0.3	16	V
	SW1, SW2	–1	44
	SW1, SW2, transient < 50 ns		–5
	BOOT1, BOOT2, HDRV1, HDRV2		V_SW + 6.0
	All other pins	–0.3	6.0
Output current	RT		200	µA
T_J	Operating junction temperature	–40	150	°C
T_stg	Storage temperature	–55	150	°C

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	3000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Input voltage	VDD, UVLO ≤ VDD	–0.3		15	V
	SW1, SW2	–1		40
	BOOT1, BOOT2, HDRV1, HDRV2		V_S_W + 5.5
	All other pins	–0.3		5.5
Maximum output current	RT		25		µA
Operating free-air temperature		–40		85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS40140	UNIT
		RHH (VQFN)
		36 PINS
R_θJA	Junction-to-ambient thermal resistance	30.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.4
R_θJB	Junction-to-board thermal resistance	5.9
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	5.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

–40°C ≤ T_J ≤ 85°C, (unless otherwise noted), V_VDD = 7 V, V_BP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5,
ƒ_SW = 300 kHz, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VDD INPUT SUPPLY
	Operating voltage range		4.5	12	15	V
	Shutdown current	UVLO_CE1 = UVLO_CE2 = GND		1	10	µA
BP5 INPUT SUPPLY
	Operating voltage range		4.5	5.0	5.5	V
	BP5 operating current		2	3	5	mA
	Rising BP5 turnon		4.0	4.25	4.45	V
	BP5 turnoff hysteresis		100	220	400	mV
	Standby mode current⁽¹⁾	UVLO_CEx = 1.7 V		2.8		mA
VREG
		7 V < V_DD < 15 V	4.5	5.1	5.5	V
		Output current	0		100	mA
OSCILLATOR, RT
	Phase frequency accuracy	R_RT= 110 kΩ		300		kHz
	Phase frequency set range		150		1000	kHz
	RT⁽¹⁾	25 kΩ ≤ R_RT ≤ 500 kΩ		0.7		V
UNDERVOLTAGE LOCKOUT (UVLO_CE1, UVLO_CE2)
	Enable threshold, standby mode	Internal 5VREG regulator enabled	0.5	1.0	1.5	V
	UVLO threshold	PWM Switching enabled	1.9	2	2.1	V
	UVLO hysteresis	At the UVLO_CEx pin		40		mV
	UVLO_CE1, UVLO_CE2 bias current⁽¹⁾				1	μA
PWM
D_MAX	Maximum duty cycle per channel⁽¹⁾	2-phase, 4-phase, 8-phase, or 16-phase		87.5%
D_MAX	Maximum duty cycle per channel⁽¹⁾	3-phase, 6-phase, or 12-phase		83.3%
t_ON(min)	Minimum controllable pulse width				70	ns
PWM COMPARATOR
	Input offset voltage		–3		3	mV
VSHARE
		I_VSHR = 0	1.785	1.8	1.815	V
	See⁽¹⁾	–30 μA < i_VSHR < 50 μA	1.785	1.8	1.815	V
ERROR AMPLIFIER CH1, ERROR AMPLIFIER CH2
	Input common mode range⁽¹⁾		0	0.7	2.0	V
	Input bias current⁽¹⁾	V_FB= 0.7 V		10		nA
	FBx voltage⁽¹⁾		0.6965	0.700	0.7035	V
	Output source current	V_COMP = 1.1 V, V_FB = 0.6 V	1	2		mA
	Output sink current	V_COMP = 1.1 V, V_FB = BP5	1	2		mA
	BW⁽¹⁾		8	12		MHz
	Open loop gain⁽¹⁾		60	90		dB
VOLTAGE TRACKING (TRK1, TRK2)
	SS source current	After EN, before PWM and during hiccup mode	5	6.0	7.3	µA
	SS source current	After first PWM pulse	10	12.5	15	µA
	Fault enable threshold⁽¹⁾			1.4		V
	Internal clamp voltage⁽¹⁾			2.4		V
	SS sink resistance⁽¹⁾	Pulldown resistance			1	kΩ
CURRENT SENSE AMPLIFIERS (CS1, CS2)
	Differential input voltage		–60		60	mV
	Input offset voltage	CS1, CS2, trimmed	–2.0	0	2.0	mV
Ac	Gain transfer to PWM COMP	5 mV < V_CS < 60 mV, V_CSRT = 1.5 V	12	13	14	V/V
	Input common mode⁽¹⁾		0		5.8	V
CSA	Input bias current			100		nA
DIFFERENTIAL AMPLIFIER (DIFFO)
	Gain	1.0 V < V_OUT < 5.8 V	0.997	1	1.003	V/V
	Input common mode range⁽¹⁾		0		5.8	V
	Output source current⁽¹⁾	V_OUT – V_VGSNS = 2 V, V_DIFFO > 1.98 V, VDD-V_OUT > 2 V			2	mA
	Output source current⁽¹⁾	V_OUT – V_VGSNS = 2 V, V_DIFFO > 2.02 V VDD – V_OUT = 1 V			1
	Output sink current⁽¹⁾	V_OUT – V_VGSNS = 2 V, V_DIFFO > 2.02 V			2
	Unity gain bandwidth⁽¹⁾		5	8		MHz
	Input Impedance, non inverting⁽¹⁾	V_OUT to GND		60		kΩ
	Input Impedance, inverting⁽¹⁾	GSNS to DIFFO		60		kΩ
GATE DRIVERS
	HDRV1, HDRV2 source on-resistance	V_BOOT1, V_BOOT2 = 5 V, V_SW1 = V_SW2 = 0 V, Sourcing 100 mA	1	2	3	Ω
	HDRV1, HDRV2 sink on-resistance	V_VREG= 5 V, V_SW1 = V_SW2 = 0 V, Sinking 100 mA	0.5	1.2	2
	LDRV1, LDRV2 source on-resistance	V_VREG= 5 V, V_SW1 = V_SW2 = 0 V, Sourcing 100 mA	1	2	3
	LDRV1, LDRV2 sink on-resistance	V_VREG = 5 V, V_SW1 = V_SW2 = 0 V, Sinking 100 mA	0.3	0.65	1
t_RISE	HDRVx rise time⁽¹⁾	C_LOAD= 3.3 nF		25	75	ns
t_FALL	HDRVx fall time⁽¹⁾	C_LOAD= 3.3 nF		25	75
t_RISE	LDRVx rise time⁽¹⁾	C_LOAD= 3.3 nF		25	75
t_FALL	LDRVx fall time⁽¹⁾	C_LOAD= 3.3 nF		20	60
	Minimum controllable on-time	C_LOAD= 3.3 nF		50
OUTPUT UNDERVOLTAGE FAULT
		V_FB relative to V_REF	–19%	–16.5%	–14%
	Undervoltage delay⁽¹⁾			3		µs
CURRENT LIMIT
I_ILIM	Output current		18.8	20	21.2	µA
POWER GOOD
	PGOOD transition low threshold	V_FB rising relative to V_REF	10%	12.5%	15%
	PGOOD transition low threshold	V_FB falling relative to V_REF	–15%	–12.5%	–10%
	PGOOD trip hysteresis		2%		5%
	PGOOD delay⁽¹⁾			10		µs
	Low level output voltage, VOL	I_PGOOD = 4 mA		0.35	0.4	V
	PGOOD bias current	V_PGOOD= 5.0 V	–2	1	2	µA
RAMP
	Ramp amplitude⁽¹⁾		0.421	0.5	0.526	V
VIN BALANCE
	V_INbalance gain, A_VB		0.23	0.25	0.27	V/V
THERMAL SHUTDOWN
	Shutdown temperature⁽¹⁾		155			°C
	Hysteresis⁽¹⁾			30		°C
DIGITAL CLOCK SIGNAL (CLKIO)
	Pullup resistance⁽¹⁾	I_OH = 5 mA		27		Ω
	Pulldown resistance⁽¹⁾	I_OL = 10 mA		27		Ω
	Output leakage⁽¹⁾	Tri-state			1	µA