SLUS660I September 2005 – January 2015 TPS40140
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
-
9 Application and Implementation
- 9.1
Application Information
- 9.1.1 Synchronizing a Single Controller to an External Clock
- 9.1.2 Split Input Voltage Operation
- 9.1.3 Configuring Single and Multiple ICs
- 9.1.4 Digital Clock Synchronization
- 9.1.5 Typical Start-Up Sequence
- 9.1.6 Track (Soft-Start Without PreBiased Output)
- 9.1.7 Soft-Start With PreBiased Outputs
- 9.1.8 Track Function in Configuring a Slave Channel
- 9.1.9 Differential Amplifier, U9
- 9.1.10 Setting the Output Voltage
- 9.1.11 Programmable Input UVLO Protection
- 9.1.12 CLKFLT, CLKIO Pin Fault
- 9.1.13 PHSEL Pin Fault
- 9.1.14 Overtemperature
- 9.1.15 Fault Masking Operation
- 9.1.16 Setting the Switching Frequency
- 9.1.17 Current Sense
- 9.1.18 Current Sensing and Balancing
- 9.1.19 Overcurrent Detection and Hiccup Mode
- 9.1.20 Calculating Overcurrent Protection Level
- 9.1.21 Design Examples Information
- 9.2
Typical Application
- 9.2.1
Application 1: Dual-Output Configuration from 12 to 3.3 V and 1.5 V DC-DC Converter Using a TPS40140
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Step 1: Inductor Selection
- 9.2.1.2.2 Step 2: Output Capacitor Selection
- 9.2.1.2.3 Step 3: Input Capacitor Selection
- 9.2.1.2.4 Step 4: MOSFET Selection
- 9.2.1.2.5
Step 5: Peripheral Component Design
- 9.2.1.2.5.1 Switching Frequency Setting (RT Pin 5)
- 9.2.1.2.5.2 Output Voltage Setting (FB1 Pin 36)
- 9.2.1.2.5.3 Current Sensing Network Design (CS1 Pin 31 and CSRT1 Pin 32)
- 9.2.1.2.5.4 Overcurrent Protection (ILIM1 Pin 34)
- 9.2.1.2.5.5 VREG (Pin 21)
- 9.2.1.2.5.6 BP5 (Pin 8)
- 9.2.1.2.5.7 PHSEL (Pin 4)
- 9.2.1.2.5.8 VSHARE (Pin 6)
- 9.2.1.2.5.9 PGOOD1 (Pin 30)
- 9.2.1.2.5.10 UVLO_CE1 (Pin 29)
- 9.2.1.2.5.11 Clkio (Pin 28)
- 9.2.1.2.5.12 BOOT1 and SW1 (Pin 27 and 25)
- 9.2.1.2.5.13 TRK1 (Pin 33)
- 9.2.1.2.5.14 DIFFO, VOUT, and GSNS (Pin 1, Pin 2, and Pin 3)
- 9.2.1.2.6 Feedback Compensator Design (COMP1 Pin 35)
- 9.2.1.3 Application Curves
- 9.2.2
Application 2: Two-Phase Single Output Configuration from 12 to 1.5 V DC-DC Converter Using a TPS40140
- 9.2.2.1 Design Requirements
- 9.2.2.2
Detailed Design Procedure
- 9.2.2.2.1 Step 1: Output Capacitor Selection
- 9.2.2.2.2 Step 2: Input Capacitor Selection
- 9.2.2.2.3
Step 3: Peripheral Component Design
- 9.2.2.2.3.1 Switching Frequency Setting (Rt Pin 5)
- 9.2.2.2.3.2 COMP1 and COMP2 (Pin 35 and Pin 10)
- 9.2.2.2.3.3 TRK1 and TRK2 (Pin 33 and Pin 12)
- 9.2.2.2.3.4 ILIM1 and ILIM2 (Pin 34 and Pin 11)
- 9.2.2.2.3.5 FB1 and FB2 (Pin 36 and Pin 9)
- 9.2.2.2.3.6 PHSEL (Pin 4)
- 9.2.2.2.3.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15)
- 9.2.2.2.3.8 CLKIO (Pin 28)
- 9.2.2.2.3.9 DIFFO, VOUT, and GSNS (Pin 1, Pin 2, and Pin 3)
- 9.2.3 Application Curves
- 9.2.1
Application 1: Dual-Output Configuration from 12 to 3.3 V and 1.5 V DC-DC Converter Using a TPS40140
- 9.3
System Example
- 9.3.1
Four-Phase Single Output Configuration from 12 to 1.8 V DC-DC Converter Using Two TPS40140
- 9.3.1.1 Step 1: Output Capacitor Selection
- 9.3.1.2 Step 2: Input Capacitor Selection
- 9.3.1.3
Step 3: Peripheral Component Design
- 9.3.1.3.1
Master Module
- 9.3.1.3.1.1 Rt (Pin 5)
- 9.3.1.3.1.2 COMP1 and COMP2 (Pin 35 and Pin 10)
- 9.3.1.3.1.3 TRK1 and TRK2 (Pin 33 and Pin 12)
- 9.3.1.3.1.4 ILIM1 and ILIM2 (Pin 34 and Pin 11)
- 9.3.1.3.1.5 FB1 and FB2 (Pin 36 and Pin 9)
- 9.3.1.3.1.6 PHSEL (Pin 4)
- 9.3.1.3.1.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15)
- 9.3.1.3.1.8 CLKIO (Pin 28)
- 9.3.1.3.2
Slave Module:
- 9.3.1.3.2.1 RT (Pin 5)
- 9.3.1.3.2.2 COMP1 and COMP2 (Pin 35 and Pin 10)
- 9.3.1.3.2.3 TRK1 and TRK2 (Pin 33 and Pin 12)
- 9.3.1.3.2.4 ILIM1 and ILIM2 ( Pin 34 and Pin 11)
- 9.3.1.3.2.5 FB1 and FB2 (Pin 36 and Pin 9)
- 9.3.1.3.2.6 PHSEL (Pin 4)
- 9.3.1.3.2.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15)
- 9.3.1.3.2.8 CLKIO (Pin 28)
- 9.3.1.3.1
Master Module
- 9.3.1
Four-Phase Single Output Configuration from 12 to 1.8 V DC-DC Converter Using Two TPS40140
- 9.1
Application Information
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
12 Device and Documentation Support
12.1 Device Support
Table 9. Definition of Symbols
| PARAMETER | DESCRIPTION |
|---|---|
| VIN(min) | Minimum operating input voltage |
| VIN(max) | Maximum operating input voltage |
| VOUT | Output voltage |
| IRIPPLE | Inductor peak-peak ripple current |
| ITRAN(MAX) | Maximum load transient |
| VUNDER | Output voltage undershot |
| VOVER | Output voltage overshot |
| VRIPPLE(TotOUT) | Total output ripple |
| VRIPPLE(COUT) | Output voltage ripple due to output capacitance |
| VRIPPLE(CIN) | Input voltage ripple due to input capacitance |
| VRIPPLE(CinESR) | Input voltage ripple due to the ESR of input capacitance |
| Pswcond | High-side MOSFET conduction loss |
| Iswrms | RMS current in the high-side MOSFET |
| Rdson(sw) | ON drain-source resistance of the high-side MOSFET |
| Pswsw | High-side MOSFET switching loss |
| Ipk | Peak current through the high-side MOSFET |
| Rdrv | Driver resistance of the high-side MOSFET |
| Qgdsw | Gate to drain charge of the high-side MOSFET |
| Qgssw | Gate to source charge of the high-side MOSFET |
| Vgsw | Gate drive voltage of the high-side MOSFET |
| Pswgate | Gate drive loss of the high-side MOSFET |
| Qgsw | Gate charge of the high-side MOSFET |
| Pswtot | Total losses of the high-side MOSFET |
| Psrcond | Low-side MOSFET conduction loss |
| Isrrms | RMS current in the low-side MOSFET |
| Rdson(sr) | ON drain-source resistance of the low-side MOSFET |
| Psrgate | Gate drive loss of the low-side MOSFET |
| Qgsr | Gate charge of the low-side MOSFET |
| Vgsr | Gate drive voltage of the low-side MOSFET |
| Pdiode | Power loss in the diode |
| td | Dead time between the conduction of high- and low-side MOSFET |
| Vf | Forward voltage drop of the body diode of the low-side MOSFET |
| Psrtot | Total losses of the low-side MOSFET |
| DCR | Inductor DC resistance |
| Ac | The gain of the current sensing amplifier, typically 13 |
| ROUT | Output load resistance |
| Vramp | Ramp amplitude, typically 0.5 V |
| T | Switching period |
| Gvc(s) | Control to output transfer function |
| Gc(s) | Compensator transfer function |
| Tv(s) | Loop gain transfer function |
| Acm | Gain of the compensator |
| fp | The pole frequency of the compensator |
| fz | The zero frequency of the compensator |
12.2 Documentation Support
12.2.1 Related Documentation
These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com
- Under The Hood of Low Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series
- Understanding Buck Power Stages in Switchmode Power Supplies (SLVA057) March 1999
- Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series
- Designing Stable Control Loops, SEM 1400, 2001 Seminar Series
- Additional PowerPAD information may be found in Applications Briefs (SLMA002) and (SLMA004)
- QFN/SON PCB Attachment, Texas Instruments (SLUA271), June 2002
12.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.