Table 6-1 summarizes the various functional modes of the device.
Table 6-1 Truth Table
| VDD |
SENSE(1) |
RESET |
RESET |
| VDD < VPOR |
— |
Undefined |
Undefined |
| VPOR < VDD <
VDD(MIN)(2) |
— |
L |
H |
| VDD ≥ VDD(MIN) |
VSENSE <
VIT- |
L |
H |
| VDD ≥ VDD(MIN) |
VSENSE > VIT- +
VHYS |
H |
L |
(1) SENSE pin voltage must be less than VIT- for the sense delay
set by CTS or greater than VIT- + VHYS for the reset delay set by
CTR before RESET transistions
(2) When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes
effect and RESET is held logic low (RESET is held logic high) until
VDD falls below VPOR at which the RESET/RESET
output is undefined.