Make sure that the connection to the VDD pin is low impedance. Good analog
design practice is to place a greater than 0.1 μF ceramic capacitor as near as
possible to the VDD pin.
To further improve the noise immunity on the
SENSE pins, placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can reduce
the sensitivity to transient voltages on the monitored signal.
If a capacitor is used on CTS or CTR, place these components as close as
possible to the respective pins. If the capacitor adjustable pins are left
unconnected, make sure to minimize the amount of parasitic capacitance on the
pins to less than 5 pF.
For open-drain variants, place the pull-up resistors on
RESET as close to the pin as possible.
When laying out metal traces,
separate high voltage traces from low voltage traces as much as possible. If
high and low voltage traces need to run close by, spacing between traces should
be greater than 20 mils (0.5 mm).
Do not have high voltage metal
pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or
traces.