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ZHCSO90A november 2022 – april 2023 TPS36-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DDF|8
- MPDS569D

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

At 1.04 V ≤ V_DD ≤ 6 V, MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, WDO pull-up resistor (R_pull-up) = 100 kΩ to VDD, output load (C_LOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/μs. Typical values are at T_A = 25℃

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
COMMON PARAMETERS
V_DD	Input supply voltage	Active LOW output		1.04		6	V
V_IT–	Negative-going input threshold accuracy ⁽¹⁾	V_IT– = 1.05 V to 1.95 V		–1.4	±0.5	1.4	%
V_IT–	Negative-going input threshold accuracy ⁽¹⁾	V_IT– = 2.0 V to 5.4 V		–1.2	±0.5	1.2	%
V_HYS	Hysteresis V_IT– pin	V_IT– = 1.05 V to 5.4 V		3	5	7	%
I_DD	Supply current into VDD pin ⁽²⁾	V_DD = 2 V V_IT– = 1.05 V to 1.95 V	T_A = –40℃ to 85℃		0.25	0.8	μA
		V_DD = 2 V V_IT– = 1.05 V to 1.95 V			0.25	3
		V_DD = 6 V V_IT– = 1.05 V to 5.4 V	T_A = –40℃ to 85℃		0.25	0.8
		V_DD = 6 V V_IT– = 1.05 V to 5.4 V			0.25	3
V_IL	Low level input voltage WD–EN, WDI, SETx, MR⁽³⁾					0.3V_DD	V
V_IH	High level input voltage WD–EN, WDI, SETx, MR⁽³⁾			0.7V_DD			V
R_MR	Manual reset internal pull-up resistance				100		kΩ
RESET / WDO (Open-drain active-low)
V_OL	Low level output voltage	V_DD =1.5 V, 1.55 V ≤ V_IT– ≤ 3.35 V I_OUT(Sink) = 500 μA				300	mV
V_OL	Low level output voltage	V_DD = 3.3 V, 3.4 V ≤ V_IT– ≤ 5.4 V I_OUT(Sink) = 2 mA				300	mV
I_lkg(OD)	Open-Drain output leakage current	V_DD = V_PULLUP = 6V T_A = –40℃ to 85℃			10	30	nA
I_lkg(OD)	Open-Drain output leakage current	V_DD = V_PULLUP = 6V			10	120	nA
RESET / WDO (Push-pull active-low)
V_POR	Power on RESET voltage ⁽⁵⁾	V_OL(max) = 300 mV I_OUT(Sink) = 15 μA				900	mV
V_OL	Low level output voltage	V_DD = 0.9 V, 1.05 V ≤ V_IT– ≤ 1.5 V I_OUT(Sink) = 15 μA				300	mV
		V_DD = 1.5 V, 1.55 V ≤ V_IT– ≤ 3.35 V I_OUT(Sink) = 500 μA				300
		V_DD = 3.3 V, 3.4 V ≤ V_IT– ≤ 5.4 V I_OUT(Sink) = 2 mA				300
V_OH	High level output voltage	V_DD= 1.8 V, 1.05 V ≤ V_IT– ≤ 1.4 V I_OUT(Source) = 500 μA		0.8V_DD			V
		V_DD= 3.3 V, 1.45 V ≤ V_IT– ≤ 3.0 V I_OUT(Source) = 500 μA		0.8V_DD
		V_DD= 6 V, 3.05 V ≤ V_IT– ≤ 5.4 V I_OUT(Source) = 2 mA		0.8V_DD

(1) V_IT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.

(2) If the logic signal driving MR is less than V_DD, then additional current flows into V_DDand out of MR.

(3) V_POR is the minimum V_DD voltage level for a controlled output state