The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated.

The output will be asserted for t_D time when any relevant events described above are detected. The time t_D can be programmed by connecting a capacitor between CRST pin and GND or device will assert t_D for fixed time duration as selected by orderable part number. Refer Section 5 section for all available options.

Equation 2 describes the relationship between capacitor value and the time t_D. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.

TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the V_IT- + V_HYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x V_DD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. Figure 8-13 shows timing behavior of the device with latched output configuration.

Figure 8-13 Output Latch Timing Behavior