ZHCSIK0A July 2018 – October 2021 TPS3430
PRODUCTION DATA
The Watchdog Window is set via the CWD, SET0, and SET1 pin configurations. To achieve a Watchdog Timeout of 1 second corresponding to a 1-Hz WDI signal, this design simply leaves CWD pin floating (NC - No Connect) and ties SET0 and SET1 to VDD to set the SET pins to logic high. With this configuration, the Watchdog Lower Boundary tWDL (typ) is set for 800 ms and the Watchdog Upper Boundary tWDU (typ) is set for 1.6 seconds. Refer to Table 6.6 Timing Requirements to see the factory-programmed window watchdog timing configurations.