ZHCSIK0A July 2018 – October 2021 TPS3430
PRODUCTION DATA
| PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
|---|---|---|
| Watchdog Reset delay | Minimum reset delay of 250 ms | Minimum reset delay of 260 ms, reset delay of 322 ms (typical) |
| Watchdog window | Functions with a 30-Hz pulse-width modulation (PWM) signal with a 50% duty cycle | Leaving the CWD pin unconnected with SET0 = 0 and SET1 = 0 produces a window with a tWDL(max) of 25.9 ms and a tWDU(min) of 46.8 ms |
| Output logic voltage | 1.8-V CMOS | 1.8-V CMOS |
| Maximum device current consumption | 200 μA | 10 μA of current consumption, typical worst-case of 199 μA when WDO is asserted |