ZHCSOF9B april 2022 – june 2023 TPS25981
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Undervoltage Lockout (UVLO and UVP)
- 8.3.2 Overvoltage Lockout (OVLO)
- 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
- 8.3.4 Analog Load Current Monitor
- 8.3.5 Overtemperature Protection (OTP)
- 8.3.6 Fault Response and Indication (FLT)
- 8.3.7 Power Good Indication (PG)
- 8.3.8 Quick Output Discharge (QOD)
- 8.3.9 Reverse Current Blocking FET Driver
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RPW|10
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.7 Power Good Indication (PG)
The TPS259814x provides an active high digital output (PG) which serves as a power good indication signal and is asserted high when the device is in steady-state and ready to deliver power. The PG is an open-drain pin and must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the FET is turned on in a controlled manner. When the FET gate voltage reaches the full overdrive indicating that the inrush sequence is complete, the PG is asserted after a de-glitch time (tPGA).
PG is de-asserted if at any time the FET is turned off. The PG de-assertion de-glitch time is tPGD.
Figure 8-7 TPS25981xx PG Timing
DiagramEvent | Protection Response | PG Pin | PG Delay |
|---|---|---|---|
Undervoltage (UVP or UVLO) | Shutdown | L | |
Overvoltage (OVLO) | Shutdown | L | tPGD |
Steady-state | NA | H | tPGA |
Transient overcurrent | NA | H | |
Persistent overload | Circuit-breaker | L | tITIMER + tPGD |
Output short-circuit to GND | Fast-trip followed by current limit | L | tPGD |
ILM pin open | Shutdown | L | tITIMER + tPGD |
ILM pin shorted to GND | Shutdown | L | tPGD |
Overtemperature | Shutdown | L | tPGD |
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.