For all applications, TI recommends a ceramic
decoupling capacitor of 0.1 μF or greater between the IN terminal and GND
terminal.
The optimal placement of the decoupling capacitor is closest to the IN and GND
terminals of the device. Care must be taken to minimize the loop area formed by
the bypass-capacitor connection, the IN terminal, and the GND terminal of the
IC.
High current-carrying power-path connections must be as short as possible and
must be sized to carry at least twice the full-load current.
The GND terminal must be tied to
the PCB ground plane at the terminal of the IC with the shortest possible trace.
The PCB ground must be a copper plane or island on the board. TI recommends to
have a separate ground plane island for the eFuse. This plane does not carry any
high currents and serves as a quiet ground reference for all the critical analog
signals of the eFuse. The device ground plane must be connected to the system
power ground plane using a star connection.
The IN and OUT pins are used for heat dissipation. Connect to as much copper
area on top and bottom PCB layers using as possible with thermal vias. The vias
under the device also help to minimize the voltage gradient across the IN and
OUT pads and distribute current uniformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
RILM
CdVdT
CITIMER
Resistors for the EN/UVLO, OVLO/OVCSEL, and PGTH pins
Connect the other end of the
component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as
short as possible to reduce parasitic effects on the current limit, overcurrent
blanking interval and soft start timing. It's recommended to keep parasitic
capacitance on ILM pin below 50 pF to ensure stable operation. These traces must
not have any coupling to switching signals on the board.
Because the bias current on ILM pin directly controls the overcurrent protection
behavior of the device, the PCB routing of this node must be kept away from any
noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed
physically close to the device they are intended to protect. These protection
devices must be routed with short traces to reduce inductance. For example, TI
recommends a protection Schottky diode to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling
capacitor of 1 μF or greater between OUT and GND. These components must be
physically close to the OUT pins. Care must be taken to minimize the loop area
formed by the Schottky diode/bypass-capacitor connection, the OUT pin, and the
GND terminal of the IC.