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ZHCSLZ4D May 2020 – September 2021 TPS25850-Q1 , TPS25851-Q1 , TPS25852-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RPQ|25
- MPQF555A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN = 13.5 V, f_SW =2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (IN PIN)
I_SD	Shutdown quiescent current; measured at IN pin.	VEN/UV = 0, -40C ≤ T_J ≤ 85C		34	63	uA
I_Q	Operating quiescent current (DCDC disable)	V_EN=V_SENSE, CCx=open, -40C ≤ T_J ≤ 85C			200	μA
V_{OVLO_R}	Voltage on VIN pin when buck regulator stops switching		26.6	27.5	28.4	V
V_{OVLO_HYS}	Hysteresis			0.5		V
ENABLE AND UVLO (EN/UVLO PIN)
V_{EN/UVLO_R}	Rising threshold for not in External UVLO	V_EN/UV rising threshold	1.26	1.3	1.34	V
V_{EN/UVLO_HYS}	Hysteresis	V_EN/UVLO falling		100		mV
V_{PA/B_EN_H}	PA_EN, PB_EN input level required to turn on PA_BUS and PB_BUS Load Switch (TPS25852-Q1)	V_{PA_EN} or V_{PB_EN} rising threshold		1.6	1.98	V
V_{PA/B_EN_L}	PA_EN, PB_EN input level required to turn off PA_BUS and PB_BUS Load Switch (TPS25852-Q1)	V_{PA_EN} or V_{PB_EN} falling threshold	0.97	1.5		V
V_{EN1/2_HYS}	Hysteresis(TPS25852-Q1)	V_{PA_EN} or V_{PB_EN} falling threshold		100		mV
BOOTSTRAP
V_{BTST_UVLO}	Bootstrap voltage UVLO threshold			2.2		V
R_BOOT	Bootstrap pull-up resistence	VSENSE-BOOT=0.1V		7.7		?
BUCK REGULATOR
I_L-SC-HS	High-side current limit	BOOT-SW=5V	10.2	11.4	12.6	A
I_L-SC-LS	Low-side current limit	SENSE=5V	8.5	10	11.5	A
I_L-NEG-LS	Low-side negative current limit	SENSE=5V	-7	-5	-3	A
I_ZC	Zero current detector threshold			0.01		A
V_SENSE	BUCK Output voltage	CC1 or CC2 pulldown resistance = R_d, VSET float or pull up to V_SENSE, T_J=25℃	-1%	5.1	+1%	V
		CC1 or CC2 pulldown resistance = R_d, VSET short to AGND, T_J=25℃	-1%	5.17	+1%	V
		CC1 or CC2 pulldown resistance = R_d, R_VSET =40.2K?, T_J=25℃	-1%	5.3	+1%	V
		CC1 or CC2 pulldown resistance = R_d, R_VSET =80.6K?, T_J=25℃	-1%	5.4	+1%	V
V_SENSE	BUCK Output voltage accuracy	CC1 or CC2 pulldown resistance = R_d, -40℃≤ T_J≤150℃	–2		2	%
V_{DCDC_UVLO_R}	SENSE input level to enable DCDC switching	V_SENSE rising, CC1 or CC2 pull down resistance = R_d	3.85	4	4.15	V
V_{DCDC_UVLO_HYS}	Hysteresis	V_SENSE falling, CC1 or CC2 pull down resistance = R_d		0.4		V
V_DROP	Dropout voltage ( V_IN-V_SENSE)	V_IN = V_SENSE+ V_DROP,V_SENS= 5.1V, I_{PA_BUS}=3A, I_{PB_BUS}=3A		300		mV
R_DS-ON-HS	High-side MOSFET ON-resistance	I_{PA_BUS}=3A, I_{PB_BUS}=3A, BOOT-SW=5V, -40℃≤ T_J≤150℃		18	34	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	I_{PA_BUS}=3A, I_{PB_BUS}=3A, V_SENSE=5V, -40℃≤ T_J≤150℃		9.5	18.5	mΩ
POWER SWITCH AND CURRENT LIMIT
R_{DS-ON_USB}	USB Load Switch MOSFET ON-resistance	I_{PA_BUS}=3A, I_{PB_BUS}=3A; -40℃≤T_J≤150℃		6.8	11.73	mΩ
R_{DS-ON_OUT}	OUT Load Switch MOSFET ON-resistance	I_OUT = 0.3 A		230		mΩ
R_{DS-ON_VCONN}	On-state resistance	T_J = 25°C, I_CCn = 0.25 A		410	550	mΩ
R_{DS-ON_VCONN}	On-state resistance	–40°C ≤T_J ≤ 150°C, I_CCn = 0.25 A		410	740	mΩ
V_{USBLS_UVLO_R}	Voltage on SENSE pin that will enable the USB Load Switch		3.95	4.1	4.25	V
V_{USBLS_UVLO_HYS}	Hysteresis			200		mV
R_{BUS_DCHG}	Discharge resistance for Port A or Port B BUS	Apply 5V on PA_BUS or PB_BUS, CC1 or CC2= Rd	250	500	750	Ω
V_{TH_R_BUS_DCHGb}	Rising threshold voltage for BUS not discharged		670	700	730	mV
V_{TH_HYS_BUS_DCHG}	Hysteresis			100		mV
V_{BUS_DCHG_BLEED}	BUS bleed resistance	V_{Px_BUS} =4V, No sink termination on CC lines, Time>t_{W_BUS_DCHG}	100	150	200	KΩ
I_{OS_HI}	BUS output short-circuit secondary current limit	R_ILIM=48.7K?	849	1061	1273	mA
		R_ILIM=19.1K?	2434	2704	2974	mA
		R_ILIM=15.4K?	3018	3354	3689	mA
		R_ILIM=12.4K?	3748	4165	4581	mA
		R_ILIM=11.5K?	4040	4490	4938	mA
		R_ILIM=9.53K?	4876	5418	5960	mA
		R_ILIM=0?(short to GND)	4828	5680	6532	mA
		R_ILIM=11.5K?, T_J=25℃	4265	4490	4714	mA
I_{OS_BUS}	BUS output short-circuit current limit	R_ILIM=48.7K?	530.4	663	800	mA
		R_ILIM=19.1K?	1521	1690	1859	mA
		R_ILIM=15.4K?	1886.4	2096	2305.6	mA
		R_ILIM=12.4K?	2342.7	2603	2863.3	mA
		R_ILIM=11.5K?	2525.4	2806	3086.6	mA
		RILIM=9.53K?	3047.4	3386	3724.6	mA
		R_ILIM=0?(short to GND)	3017.5	3550	4082.5	mA
		R_ILIM=11.5K?, T_J=25℃	2666	2806	2946	mA
I_{OS_OUT}	OUT output short-circuit current limit	Short circuit current limit	390	450	495	mA
I_{OS_VCONN}	VCONN output short-circuit current limit	Short circuit current limit	240	300	360	mA
CABLE COMPENSATION VOLTAGE
V_{DROP_COM}	Cable compensation voltage(TPS25850/1/2)	I_{PA_BUS} or I_{PB_BUS}=2.4A, VSET=GND(set 5.17V output)	70	90	110	mV
CC CONNECT MANAGEMENT
I_{SRC_CC_3A}	Sourcing current	CC pin voltage: 0 V ≤ V_CCn ≤ 2.45 V	304	330	356	μA
I_{SRC_CC_1.5A}	Sourcing current in thermal management(Temp warm)	CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V , T_A> 85℃	167	180	194	μA
I_{SRC_CC_DFLT}	Sourcing current in thermal management(Temp hot)	CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V , T_A> 85℃	64	80	105	μA
I_REV	Reverse leakage current	CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy floating, V_{EN_UV} = 0 V or V_SENSE, 0 V ≤ V_IN ≤ 26 V I_REV is current into CCx pin		2.75	10	μA
V_{TH_R}	Rising threshold voltage for VCONN not discharged	CC pin that was providing VCONN in previous SINK state	670	700	730	mV
V_{TH_HYS}	Hysteresis			100		mV
FAULT, POL(TPS25851/2-Q1)
V_OL	PA_FAULT, PB_FAULT Output low voltage (TPS25851/2-Q1)	I_{SNK_PIN} = 1 mA			250	mV
I_OFF	PA_FAULT, PB_FAULT Off-state leakage (TPS25851/2-Q1)	V_PIN = 5.5 V			2.2	μA
V_OL	PA_POL, PB_POL Output low voltage (TPS25851-Q1)	I_{SNK_PIN} = 1 mA			250	mV
I_OFF	PA_POL, PB_POL Off-state leakage (TPS25851-Q1)	V_PIN = 5.5 V			1.8	μA
BC 1.2 DOWNSTREAM CHARGING PORT (TPS25850-Q1)
R_{DPM_SHORT}	DP and DM shorting resistance			70	200	Ω
DIVIDER 3 MODE (TPS25850-Q1)
V_{DP_DIV3}	DP output voltage		2.57	2.7	2.84	V
V_{DM_DIV3}	DM output voltage		2.57	2.7	2.84	V
R_{DP_DIV3}	DP output impedance	I_{DP_IN} = –5 μA	24	30	36	kΩ
R_{DM_DIV3}	DM output impedance	I_{DM_IN} = –5 μA	24	30	36	kΩ
1.2-V MODE (TPS25850-Q1)
V_{DP_1.2V}	DP output voltage		1.12	1.2	1.26	V
V_{DM_1.2V}	DM output voltage		1.12	1.2	1.26	V
R_{DP_1.2V}	DP output impedance	I_{DP_IN} = –5 μA	84	100	126	kΩ
R_{DM_1.2V}	DM output impedance	I_{DM_IN} = –5 μA	84	100	126	kΩ
FREQ/SYNC THRESHOLD
V_{IH_FREQ/SYNC}	FREQ/SYNC high threshold for external clock synchronization	Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin)	2			V
V_{IL_FREQ/SYNC}	FREQ/SYNC low threshold for external clock synchronization	Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin)			0.8	V
TEMPERATURE SENSING
V_{WARN_HIGH}	Temperature warning threshold rising	As percentage to V_SENSE	0.475	0.5	0.525	V/V
V_{WARN_HYS}	Hysteresis	As percentage to V_SENSE		0.1		V/V
V_{HOT_HIGH}	Temperature Hot assert threshold rising to reduce SENS voltage	As percentage to V_SENSE	0.618	0.65	0.683	V/V
V_{HOT_HYS}	Hysteresis	As percentage to V_SENSE		0.1		V/V
V_{R_VSENS}	V_SENSE voltage decay when Temperature Hot assert	TS pin voltage rise above 0.65*V_SENSE		4.77		V
THERMAL SHUTDOWN
T_{LS_SD}	USB Load Switch Over Temperature	Shutdown threshold		160		°C
T_{LS_SD}	USB Load Switch Over Temperature	Recovery threshold		150		°C
T_SD	Thermal shutdown	Shutdown threshold		166		°C
T_SD	Thermal shutdown	Recovery threshold		154		°C