ZHCSHL4I October 2008 – December 2017 TPS23754 , TPS23754-1 , TPS23756
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1
PoE Overview
- 7.4.1.1 Threshold Voltages
- 7.4.1.2 PoE Start-Up Sequence
- 7.4.1.3 Detection
- 7.4.1.4 Hardware Classification
- 7.4.1.5 Inrush and Start-Up
- 7.4.1.6 Maintain Power Signature
- 7.4.1.7 Start-Up and Converter Operation
- 7.4.1.8 PD Hotswap Operation
- 7.4.1.9 Converter Controller Features
- 7.4.1.10 Bootstrap Topology
- 7.4.1.11 Current Slope Compensation and Current Limit
- 7.4.1.12 Blanking – RBLNK
- 7.4.1.13 Dead Time
- 7.4.1.14 FRS and Synchronization
- 7.4.1.15 T2P, Start-Up, and Power Management
- 7.4.1.16 Thermal Shutdown
- 7.4.1.17 Adapter ORing
- 7.4.1.18 PPD ORing Features
- 7.4.1.19 Using DEN to Disable PoE
- 7.4.1.20 ORing Challenges
- 7.4.1
PoE Overview
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Input Bridges and Schottky Diodes
- 8.2.2.2 Protection, D1
- 8.2.2.3 Capacitor, C1
- 8.2.2.4 Detection Resistor, RDEN
- 8.2.2.5 Classification Resistor, RCLS
- 8.2.2.6 Dead Time Resistor, RDT
- 8.2.2.7 Switching Transformer Considerations and RVC
- 8.2.2.8 Special Switching MOSFET Considerations
- 8.2.2.9 Thermal Considerations and OTSD
- 8.2.2.10 APD Pin Divider Network, RAPD1, RAPD2
- 8.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
- 8.2.2.12 Setting Frequency (RFRS) and Synchronization
- 8.2.2.13 Current Slope Compensation
- 8.2.2.14 Blanking Period, RBLNK
- 8.2.2.15 Estimating Bias Supply Requirements and CVC
- 8.2.2.16 T2P Pin Interface
- 8.2.2.17 Advanced ORing Techniques
- 8.2.2.18 Soft Start
- 8.2.2.19 Frequency Dithering for Conducted Emissions Control
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- PWP|20
散熱焊盤機械數據 (封裝 | 引腳)
- PWP|20
訂購信息
8.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
The PPD pin can be used to override the internal hotswap MOSFET UVLO (VUVLO_R and VUVLO_H) when using low voltage adapters connected between VDD and VSS. The PPD pin has an internal 5-μA pulldown current source. As an example, consider the choice of RPPD1 and RPPD2, for a 24-V adapter.
- Select the start-up voltage, VADPTR-ON approximately 75% of nominal for a 24-V adapter. Assuming that the adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.
- Choose VADPTR-ON = 24 V × 0.75 = 18 V.
- Choose RPPD2 = 3.01 kΩ.
- Calculate RPPD1.
- Check PPD turnon and PPD turnoff voltages.
- Voltages look acceptable.
- Check PPD resistor power consumption.
- Power is acceptable, but resistor values could be increased to reduce the power loss.
The PPD pin can also be used to modify the internal MOSFET UVLO for use with a lower output voltage PSE (within certain limits). Connect the RPPD1 and RPPD2 dividers directly between VDD and VSS with the midpoint connected to PPD. For this case and to allow classification, target the minimum PSE OFF voltage (VADPTR_OFF) > VCU_OFF = 23 V. Then follow the procedure outlined above to select RPPD1, RPPD2, and determine the PSE ON (VADPTR_ON) and PSE OFF (VADPTR_OFF) voltages ensuring that PSE OFF > 23 V. Lastly, because the RPPD1 and RPPD2 divider is in parallel with RDEN during detection, RDEN must be increased such that the equivalent detection resistance is 25 kΩ nominal.
