ZHCSF80B May 2016 – September 2017 TPS22975
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
訂購(gòu)信息
12 Layout
12.1 Layout Guidelines
For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance. The CT trace must be as short as possible to reduce parasitic capacitance.
12.2 Layout Example
Figure 34. Layout Recommendation
12.3 Thermal Considerations
The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) , for a given ambient temperature, use Equation 5 as a guideline.
where
- PD(max) is the maximum allowable power dissipation
- TJ(max) is the maximum allowable junction temperature (125°C for the TPS22975)
- TA is the ambient temperature of the device
- ΘJA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly dependent upon board layout.
In Figure 34, notice that the thermal vias are located under the exposed thermal pad of the device. This allows for thermal diffusion away from the device.