9.3.1 On/Off Control (EN pin)

The EN pin controls the state of the switch. When the voltage on EN has exceeded V_IH,EN the switch will be enabled. When EN goes below V_IL,EN the switch is disabled.

The EN pin has a blanking time of t_BLANK on the rising edge once the V_IH,EN threshold has been exceeded. It also has a deglitch time of t_DEGLITCH when the voltage has gone below V_IL,EN.

The EN pin can also be configured via an external resistor divider to monitor a voltage signal for input UVLO. Refer to the equation and diagram below on how to configure the EN pin for input UVLO.

Equation 1.

Where:

V_IH,EN = the rising threshold of the EN pin (see Electrical Characteristics table)
V_IN = the input voltage being monitored (this could be V_IN, V_BIAS, or an external power supply)
R_EN1, R_EN2 = resistor divider values

9.3.2 Voltage Monitoring (SNS pin)

The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored or be tied to OUT directly. If the voltage on the SNS pin exceeds V_IH,SNS, the voltage being monitored on the SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than V_IH,SNS for at least t_BLANK before PG is asserted high. If the voltage on the SNS pin goes below V_IL,SNS, then the switch will power cycle (i.e., the switch will be disabled and re-enabled). For proper functionality of the device, this pin must not be left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to V_OUT.

The SNS pin has a blanking time of t_BLANK on the rising edge once the V_IH,SNS threshold has been exceeded. It has a deglitch time of t_DEGLITCH when the voltage has gone below V_IL,SNS.

Refer to the equation and diagram below on how to configure the SNS pin for voltage monitoring.

Equation 2.

Where:

V_IH,SNS = the rising threshold of the SNS pin (see Electrical Characteristics table)
V_OUT = voltage on the OUTpin
R_SNS1, R_SNS2 = resistor divider values

9.3.3 Power Good (PG Pin)

The PG pin is only asserted high when the voltage on EN has exceeded V_IH,EN and the voltage on SNS has exceeded V_IH,SNS. There is a t_BLANK time, typically 100µs, between the SNS voltage exceeding V_IH,SNS and PG being asserted high. If the voltage on EN goes below V_IL,EN or the voltage on SNS goes below V_IL,SNS, PG will be de-asserted. There is a t_DEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their respective V_IL levels and PG being pulled low.

PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device functionality.

For proper PG operation, the BIAS voltage should be within the recommended operating range. In systems that are very sensitive to noise or have long PG traces, it is recommended to add a small capacitance from PG to GND to for decoupling.

9.3.4 Supervisor Fault Detection and Automatic Restart

The falling edge of the SNS pin below V_IL,SNS is considered a fault case and will cause the load switch to be disabled for t_RESTART (typically 2ms). After the t_RESTART time, the switch will be automatically re-enabled as long as EN is still above V_IH,EN . In the case the SNS pin is being used to monitor V_OUT or a downstream voltage, the restart will help to protect against excessive over-current if there is a quick short to GND.

Figure 50. Automatic Restart after Quick Short to GND

9.3.5 Manual Restart

The falling edge of the SNS pin below V_IL,SNS is considered a fault case and will cause the load switch to be disabled for t_RESTART (typically 2ms). The SNS pin can be driven by an MCU to manually reset the load switch. After the t_RESTART time, the switch will be automatically re-enabled as long as EN is still above V_IH,EN , even is SNS is held low. The PG pin will stay low until the switch is re-enabled and the SNS pin rises above V_IH,SNS.

Figure 51. Manual Restart (SNS Held Low)

If the SNS pin is brought above V_IH,SNS within the t_RESTART time, the switch will still wait to re-enable. The PG pin will also stay low until t_BLANK after switch is re-enabled. In this case, PG will indicate when the switch is enabled and capable of being reset again.

Figure 52. Manual Restart (SNS Toggled Low to High)

9.3.6 Thermal Shutdown

If the junction temperature of the device exceeds T_SD, the switch will be disabled. The device will be enabled once the junction temperature drops by TSD_HYS as long as EN is still greater than V_IH,EN.

9.3.7 Quick Output Discharge (QOD) (TPS22954 Only)

The quick output discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the recommended V_BIAS voltage is met. During this state, the QOD resistance (R_PD) will discharge V_OUT to GND. It is not recommended to apply a continuous DC voltage to OUT when the device is disabled.

The QOD transistor can remain active for a short period of time even after V_BIAS looses power. This brief period of time is defined as t_DIS. For best results, it is recommended the device get disabled before V_BIAS goes below the minimum recommended voltage. The waveform below shows the behaviour when power is applied and then removed in a typical application.

Figure 53. Power Applied and then Removed in a Typical Application

At the end of the t_DIS time, it is not guaranteed that V_OUT will be 0V since the final voltage will be dependent upon the initial voltage and the C_L capacitor. The final V_OUT can be calculated with the following formula for a given initial voltage and C_L capacitor.

Equation 3.

Where:

V_f = final V_OUT voltage
V_o = initial V_OUT voltage
R = the value of the output discharge resistor, R_PD (see Electrical Characteristics table)
C = the output bulk capacitance on OUT

9.3.8 V_IN and V_BIAS Voltage Range

For optimal R_ON performance, make sure V_IN ≤ V_BIAS. The device will still be functional if V_IN > V_BIAS but it will exhibit R_ON greater than what is listed in the Electrical Characteristics table. See Figure 50 for an example of a typical device. Notice the increasing R_ON as V_IN increases. Be sure to never exceed the maximum voltage rating for V_IN and V_BIAS.

Figure 54. R_ON When V_IN > V_BIAS

9.3.9 Adjustable Rise Time (CT pin)

A capacitor to GND on the CT pin sets the slew rate for V_OUT. An appropriate capacitance value should be placed on CT such that the I_MAX and I_PLS specifications of the device are not violated. The capacitor to GND on the CT pin should be rated for 25 V or higher. An approximate formula for the relationship between CT (except for CT = open) and the slew rate for any V_BIAS is:

Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. The table below contains rise time values measured on a typical device.