SLVSHZ1A June 2024 – July 2025 TPS1HTC100-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SNS TIMING - CURRENT SENSE | ||||||
| tSNSION1 | Settling time from rising edge of DIAG_EN 50% of VDIAG_EN to 90% of settled ISNS |
VEN= 5V, VDIAG_EN = 0V to 5V, RSNS = 1kΩ, IL = 1A |
15 | μs | ||
| VEN = 5V, VDIAG_EN = 0V to 5V, RSNS = 1kΩ, IL = 50mA |
80 | μs | ||||
| tSNSION2 | Settling time from rising edge of EN and DIAG_EN 50% of VDIAG_EN VEN to 90% of settled ISNS |
VEN = VDIAG_EN = 0V to 5V VS = 24V RSNS = 1 kΩ, IL = 1A |
200 | μs | ||
| tSNSION3 | Settling time from rising edge of EN 50% of VEN to 90% of settled ISNS |
VEN = 0V to 5V, VDIAG_EN = 5V RSNS = 1kΩ, IL = 1A |
200 | μs | ||
| tSNSIOFF | Settling time from falling edge of DIAG_EN | VEN = 5V, VDIAG_EN = 5V to 0V RSNS = 1kΩ, RL = 48Ω |
20 | μs | ||
| tSETTLEH | Settling time from rising edge of load step. |
VEN = VDIAG_EN = 5V RSNS = 1kΩ, IOUT = 0.5A to 3A |
20 | μs | ||
| tSETTLEL | Settling time from falling edge of load step. |
VEN = VDIAG_EN = 5V RSNS = 1kΩ, IOUT = 3A to 0.5A |
20 | μs | ||
| tSNSFH | Assertion time for SNSFH From 50% rising edge of VSNSFH to 50% of falling edge of VSNSFH |
VDIAG_EN = VEN = 0V to 5V RSNS = 1kΩ, IOUT = 5mA COUT =15μF |
60 | μs | ||