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SLVS640F October 2007 – February 2015 TPD12S520

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RMN|24
- MPQF394B
DBT|38
- MPDS368A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_{5V_SUPPLY}	Supply voltage	–0.3	6	V
V_{LV_SUPPLY}	Supply voltage	–0.3	6	V
V_I/O	DC voltage at any channel input	–0.5	6	V
T_A	Operating Free Air Temperature	–40	85	°C
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ⁽¹⁾	See Pin Configuration and Functions	±2000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 Contact Discharge⁽²⁾	See Pin Configuration and Functions	±8000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
T_A	Operating free-air temperature	–40		85	°C
5V_SUPPLY	Operating supply voltage	GND	5	5.5	V
LV_SUPPLY	Bias supply voltage	1	3.3	5.5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD12S520		UNIT
		DBT	RMN
		38 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	83.6	80.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.8	36.4
R_θJB	Junction-to-board thermal resistance	44.7	27.1
ψ_JT	Junction-to-top characterization parameter	2.9	1.4
ψ_JB	Junction-to-board characterization parameter	44.1	27.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
I_5V	Operating supply current	5V_SUPPLY = 5 V				1	5	µA
I_LV	Bias supply current	LV_SUPPLY = 3.3 V				1	2	mA
I_OFF	OFF-state leakage current, level-shifting NFET	LV_SUPPLY = 0 V				0.1	1	µA
I_{BACK DRIVE}	Current conducted from output pins to V_SUPPLY rails when powered down	5V_SUPPLY < V_{CH_OUT}	TMDS_D[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT			0.1	5	µA
V_ON	Voltage drop across level-shifting NFET when ON	LV_SUPPLY = 2.5 V, V_S = GND, I_DS = 3 mA			75	95	140	mV
V_F	Diode forward voltage	I_F = 8 mA,	Top diode			1		V
V_F	Diode forward voltage	T_A = 25°C⁽¹⁾	Bottom diode			1		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Positive transients			9		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Negative transients			-9		V
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Positive transients			0.6		Ω
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Negative transients			0.5		Ω
I_LEAK	TMDS channel leakage current	T_A = 25°C⁽¹⁾				0.01	1	µA
C_IN, TMDS	TMDS channel input capacitance	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.8	1.0	pF
ΔC_IN, TMDS	TMDS channel input capacitance matching	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾⁽⁴⁾				0.05		pF
C_MUTUAL	Mutual capacitance between signal pin and adjacent signal pin	5V_SUPPLY= 0 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.07		pF
C_IN	Level-shifting input capacitance, capacitance to GND	5V_SUPPLY= 0 V, Measured at 100 KHz, V_BIAS= 2.5 V⁽¹⁾		DDC		3.5	4	pF
				CEC		3.5	4
				HP		3.5	4