SLVS640F October 2007 – February 2015 TPD12S520
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 ±8-kV Contact ESD Protection on External Lines
- 7.3.2 Single-Chip ESD Solution for HDMI Driver
- 7.3.3 Supports All HDMI 1.3 and HDMI 1.4b Data Rates
- 7.3.4 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector
- 7.3.5 24-Pin WQFNPackage for Space Constrained Applications
- 7.3.6 Integrated Level Shifting for the Control Lines
- 7.3.7 Backdrive Protection
- 7.3.8 Lead-Free Package
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD12S520 provides IEC61000-4-2 Level 4 Contact ESD rating to the HDMI 1.4 receiver port. Integrated voltage-level shifting reduces the board space needed to implement the control lines.
8.2 Typical Application
TPD12S520 is designed to protect a typical HDMI 1.4 receiver port. Refer to Figure 6 for a typical schematic. The eight TMDS data lines (D2+/-, D1+/-, D0+/-, CLK+/-) each have two pins on TPD12S520 to connect to. The TMDS data lines flow through their respective pin pairs, attaching to the passive ESD protection circuitry.
Figure 6. TPD12S520 Configured with an HDMI 1.4 Receiver Port
8.2.1 Design Requirements
For this example, use the following table as input parameters:
| DESIGN PARAMETERS | EXAMPLE VALUE |
|---|---|
| Voltage on 5V_SUPPLY | 4.5 V - 5.5 V |
| Voltage on LV_SUPPLY | 1.7 V - 1.9 V |
8.2.2 Detailed Design Procedure
To begin the design process the designer needs to know the 5V_SUPPLY voltage range and the logic level, LV_SUPPLY, voltage range.
8.2.3 Application Curves
Figure 7. HDMI 1.65Gbps Eye Diagram With TPD12S520 on a Test Board
Figure 9. Test Board to Measure Eye Diagram for the TPD12S520 (Refer to Eye Diagram Plot)
Figure 8. HDMI 1.65Gbps Eye Diagram Without TPD12S520 on a Test Board