TC = 25°C, PVDD = VBAT =
14.4 V, DVDD = 3.3 V, RL = 4 ?, Pout = 1 W/ch, ?OUT
= 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, 1SPW Mode, AES17
Filter, default I2C settings, LC reconstruction filter: 3.3 μH -
ASWPA4035S3R3MT in 4Ω, ASWPA6055S3R3MT in 2 Ω configuration and 1 μF (unless
otherwise noted). See application diagram in Figure 8-2
Figure 6-25 THD+N
vs Power - BTL, 2 Ω, 4 Ω, 14.4 V, 1SPW
Figure 6-27
THD+N vs Frequency - BTL, 2 Ω, 4 Ω, 14.4 V, 1SPW
Figure 6-29
Efficiency vs Output Power - BTL, 4 Ω, 14.4 V, 1SPW
Figure 6-31
Efficiency vs Output Power - BTL, 2 Ω, 14.4 V, 1SPW
Figure 6-33 PVDD
Idle Current vs Supply Voltage - BTL, 1SPW
Figure 6-35 PVDD
Idle Current vs Supply Voltage - BTL, 1SPW, 384 kHz
Figure 6-26
THD+N vs Power - BTL, 2 Ω, 4 Ω, 18 V, 1SPW
Figure 6-28
Ouput Power vs Supply Voltage - BTL, 2 Ω, 4 Ω, 1SPW
Figure 6-30
Power Dissipation vs Output Power - BTL, 4 Ω, 14.4 V, 1SPW
Figure 6-32
Power Dissipation vs Output Power - BTL, 2 Ω, 14.4 V, 1SPW
Figure 6-34 VBAT
Idle Current vs Supply Voltage - BTL, 1SPW
Figure 6-36
Noise vs Supply Voltage - BTL, 1SPW