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ZHCSFQ5A April 2016 – November 2016 TPA3244

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDW|44

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	BST_X to GVDD_X⁽²⁾	–0.3	43	V
	VDD to GND	–0.3	13.2	V
	GVDD_X to GND⁽²⁾	–0.3	13.2	V
	PVDD_X to GND⁽²⁾	–0.3	43	V
	DVDD to GND	–0.3	4.2	V
	AVDD to GND	–0.3	8.5	V
	VBG to GND	-0.3	4.2	V
Interface pins	OUT_X to GND⁽²⁾	–0.3	43	V
	BST_X to GND⁽²⁾	–0.3	55.5	V
	OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND	–0.3	4.2	V
	RESET, FAULT, CLIP_OTW, CLIP to GND	–0.3	4.2	V
	INPUT_X to GND	–0.3	7	V
	Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to GND		9	mA
T_J	Operating junction temperature range	0	150	°C
T_stg	Storage temperature range	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

7.2 ESD Ratings

			VALUE	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ⁽¹⁾	±1000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	TYP	MAX	UNIT
PVDD_x	Half-bridge supply	DC supply voltage	12	30	31.5	V
GVDD_x	Supply for logic regulators and gate-drive circuitry	DC supply voltage	10.8	12	13.2	V
VDD	Digital regulator supply voltage	DC supply voltage	10.8	12	13.2	V
R_L(BTL)	Load impedance	Output filter inductance within recommended value range	2.7	4		Ω
R_L(SE)			1.5	3
R_L(PBTL)			1.6	2
L_OUT(BTL)	Output filter inductance	Minimum output inductance at I_OC	5			μH
L_OUT(SE)			5
L_OUT(PBTL)			5
F_PWM	PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance	Nominal	430	450	470	kHz
		AM1	475	500	525
		AM2	575	600	625
R_{(FREQ_ADJ)}	PWM frame rate programming resistor	Nominal; Master mode	29.7	30	30.3	kΩ
		AM1; Master mode	19.8	20	20.2
		AM2; Master mode	9.9	10	10.1
C_PVDD	PVDD close decoupling capacitors			1.0		μF
R_OC	Over-current programming resistor	Resistor tolerance = 5%	22		30	kΩ
R_OC(LATCHED)	Over-current programming resistor	Resistor tolerance = 5%	47		64	kΩ
V_{(FREQ_ADJ)}	Voltage on FREQ_ADJ pin for slave mode operation	Slave mode		3.3		V
T_J	Junction temperature		0		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPA3244	UNIT
		DDV 44-PINS HTSSOP
		JEDEC STANDARD 4 LAYER PCB
R_θJA	Junction-to-ambient thermal resistance	23.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	9.1	°C/W
R_θJB	Junction-to-board thermal resistance	3.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	3.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, T_A (Ambient temperature) = 25°C, f_S = 450 kHz, unless otherwise specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD	Voltage regulator, only used as reference node	VDD = 12 V	3	3.3	3.6	V
AVDD	Voltage regulator, only used as reference node	VDD = 12 V		7.8		V
I_VDD	VDD supply current	Operating, 50% duty cycle		40		mA
I_VDD	VDD supply current	Idle, reset mode		13		mA
I_{GVDD_X}	Gate-supply current per full-bridge	50% duty cycle		15		mA
I_{GVDD_X}	Gate-supply current per full-bridge	Reset mode		2		mA
I_{PVDD_X}	PVDD idle current per full bridge	50% duty cycle with 10µH Output Filter Inductors		12.5		mA
I_{PVDD_X}	PVDD idle current per full bridge	Reset mode, No switching		1		mA
ANALOG INPUTS
R_IN	Input resistance			24		kΩ
V_IN	Maximum input voltage swing				7	V
I_IN	Maximum input current				1	mA
G	Inverting voltage Gain	V_OUT/V_IN		20		dB
OSCILLATOR
f_OSC(IO+)	Nominal, Master Mode	F_PWM × 6	2.58	2.7	2.82	MHz
	AM1, Master Mode		2.85	3	3.15
	AM2, Master Mode		3.45	3.6	3.75
V_IH	High level input voltage		1.86			V
V_IL	Low level input voltage				1.45	V
OUTPUT-STAGE MOSFETs
R_DS(on)	Drain-to-source resistance, low side (LS)	T_J = 25°C, Includes metallization resistance, GVDD = 12 V		65		mΩ
R_DS(on)	Drain-to-source resistance, high side (HS)	T_J = 25°C, Includes metallization resistance, GVDD = 12 V		65		mΩ
I/O PROTECTION
V_uvp,VDD,GVDD	Undervoltage protection limit, GVDD_x and VDD			9.5		V
V_{uvp,VDD, GVDD,hyst} ⁽¹⁾				0.6		V
V_uvp,PVDD	Undervoltage protection limit, PVDD_x			10		V
V_{uvp,PVDD,hyst} ⁽¹⁾				0.6		V
OTW	Overtemperature warning, CLIP_OTW⁽¹⁾		115	125	135	°C
OTW_hyst ⁽¹⁾	Temperature drop needed below OTW temperature for CLIP_OTW to be inactive after OTW event.			25		°C
OTE⁽¹⁾	Overtemperature error		145	155	165	°C
OTE_hyst ⁽¹⁾	A reset needs to occur for FAULT to be released following an OTE event			25		°C
OTE-OTW_{(differential)} ⁽¹⁾	OTE-OTW differential			30		°C
OLPC	Overload protection counter	f_PWM = 450 kHz		2.3		ms
I_OC	Overcurrent limit protection	Resistor – programmable, nominal peak current in 1Ω load, R_OCP = 22 kΩ		14		A
I_OC(LATCHED)	Overcurrent limit protection	Resistor – programmable, peak current in 1Ω load, R_OCP = 47kΩ		14		A
I_DCspkr	DC Speaker Protection Current Threshold	BTL current imbalance threshold		1.5		A
I_OCT	Overcurrent response time	Time from switching transition to flip-state induced by overcurrent.		150		ns
I_PD	Output pulldown current of each half	Connected when RESET is active to provide bootstrap charge. Not used in SE mode.		3		mA
STATIC DIGITAL SPECIFICATIONS
V_IH	High level input voltage	M1, M2, OSC_IOP, OSC_IOM, RESET	1.9			V
V_IL	Low level input voltage	M1, M2, OSC_IOP, OSC_IOM, RESET			0.8	V
I_lkg	Input leakage current				100	μA
OTW/SHUTDOWN (FAULT)
R_{INT_PU}	Internal pullup resistance, CLIP_OTW to DVDD, FAULT to DVDD		20	26	32	kΩ
V_OH	High level output voltage	Internal pullup resistor	3	3.3	3.6	V
V_OL	Low level output voltage	I_O = 4 mA		200	500	mV
Device fanout	CLIP_OTW, FAULT	No external pullup		30		devices

(1) Specified by design.

7.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 8 Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 10 μH, C_DEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise noted.

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
P_O	Power output per channel	R_L = 8 Ω, 10% THD+N	60		W
		R_L = 4 Ω, 10% THD+N, Single Channel, 20 seconds duration⁽¹⁾	110
		R_L = 8 Ω, 1% THD+N	50
		R_L = 4 Ω, 1% THD+N, 3 seconds Peak Power⁽¹⁾	90
		R_L = 4 Ω, 1% THD+N, Single Channel, 40 seconds Peak Power⁽¹⁾	90
THD+N	Total harmonic distortion + noise	1 W	0.005%
V_n	Output integrated noise	A-weighted, AES17 filter, Input Capacitor Grounded	60		μV
\|V_OS\|	Output offset voltage	Inputs AC coupled to GND	20	60	mV
SNR	Signal-to-noise ratio⁽²⁾		111		dB
DNR	Dynamic range		111		dB
P_idle	Power dissipation due to Idle losses (I_{PVDD_X})	P_O = 0, 4 channels switching⁽³⁾	0.38		W

(1) Peak Power rating using TPA3244 EVM

(2) SNR is calculated relative to 1% THD+N output level.

(3) Actual system idle losses also are affected by core losses of output inductors.

7.7 Audio Characteristics (SE)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 4 Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 15 μH, C_DEM = 1 µF, MODE = 11, AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER		TEST CONDITIONS	TYP	UNIT
P_O	Power output per channel	R_L = 4 Ω, 10% THD+N	30	W
		R_L = 3 Ω, 10% THD+N	39
		R_L = 4 Ω, 1% THD+N	25
		R_L = 3 Ω, 1% THD+N	32
THD+N	Total harmonic distortion + noise	1 W	0.01%
V_n	Output integrated noise	A-weighted, AES17 filter, Input Capacitor Grounded	100	μV
SNR	Signal to noise ratio⁽¹⁾	A-weighted	100	dB
DNR	Dynamic range	A-weighted	101	dB
P_idle	Power dissipation due to idle losses (IPVDD_X)	P_O = 0, 4 channels switching⁽²⁾	0.38	W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

7.8 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 4 Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 10 μH, C_DEM = 1 µF, MODE = 10, outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER		TEST CONDITIONS	TYP	UNIT
P_O	Power output per channel	R_L = 4 Ω, 10% THD+N	125	W
		R_L = 3 Ω, 10% THD+N	160
		R_L = 4 Ω, 1% THD+N	100
		R_L = 3 Ω, 1% THD+N	130
THD+N	Total harmonic distortion + noise	1 W	0.005%
V_n	Output integrated noise	A-weighted, AES17 filter, Input Capacitor Grounded	55	μV
SNR	Signal to noise ratio⁽¹⁾	A-weighted	112	dB
DNR	Dynamic range	A-weighted	112	dB
P_idle	Power dissipation due to idle losses (IPVDD_X)	P_O = 0, 4 channels switching⁽²⁾	0.38	W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

7.9 Typical Characteristics

7.9.1 BTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 8 Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 10 μH, C_DEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise noted.

R_L = 4 Ω	P = 1W, 20W, 60W	T_A = 25°C

Figure 1. Total Harmonic Distortion+Noise vs Frequency

R_L =4 Ω, 8 Ω

T_A = 25°C

Figure 3. Total Harmonic Distortion + Noise vs Output Power

R_L = 4 Ω, 8 Ω

THD+N = 1%

T_A = 25°C

Figure 5. Output Power vs Supply Voltage

R_L = 4 Ω, 8 Ω		T_A = 25°C

Figure 7. System Power Loss vs Output Power

R_L = 4 Ω	P = 1W, 20W, 60W	T_A = 25°C
AUX-0025 filter, 80 kHz analyzer BW

Figure 2. Total Harmonic Distortion+Noise vs Frequency

R_L = 4 Ω, 8 Ω

THD+N = 10%

T_A = 25°C

Figure 4. Output Power vs Supply Voltage

R_L = 4 Ω, 8 Ω

T_A = 25°C

Figure 6. System Efficiency vs Output Power

8 Ω, V_REF = 25.46 V (1% Output power)			FFT = 16384
AUX-0025 filter, 80 kHz analyzer BW			T_A = 25°C

Figure 8. Noise Amplitude vs Frequency

7.9.2 SE Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 4 Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 15 μH, C_DEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless otherwise noted.

R_L = 2 Ω, 3Ω, 4Ω

T_A = 25°C

Figure 9. Total Harmonic Distortion+Noise vs Output Power

R_L = 4Ω	P = 1W, 5W, 20W	T_A = 25°C
AUX-0025 filter, 80 kHz analyzer BW

Figure 11. Total Harmonic Distortion+Noise vs Frequency

R_L = 2 Ω, 3Ω, 4Ω

THD+N = 1%

T_A = 25°C

Figure 13. Output Power vs Supply Voltage

R_L = 4Ω

P = 1W, 5W, 20W

T_A = 25°C

Figure 10. Total Harmonic Distortion+Noise vs Frequency

R_L = 2 Ω, 3Ω, 4Ω	THD+N = 10%	T_A = 25°C

Figure 12. Output Power vs Supply Voltage

7.9.3 PBTL Configuration

All Measurements taken at audio frequency = 1kHz, PVDD_X = 30 V, GVDD_X = 12 V, R_L = 4Ω, f_S = 450 kHz, R_OC = 22 kΩ, T_A = 25°C, Output Filter: L_DEM = 10 μH, C_DEM = 1 µF, MODE = 10, outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.