ZHCSAA4B September 2012 – September 2015 TPA3110D2-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 TPA3110D2-Q1 Modulation Scheme
- 8.2.2.2 Ferrite Bead Filter Considerations
- 8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
- 8.2.2.4 When to Use an Output Filter for EMI Suppression
- 8.2.2.5 Input Resistance
- 8.2.2.6 Input Capacitor, CI
- 8.2.2.7 BSN and BSP Capacitors
- 8.2.2.8 Differential Inputs
- 8.2.2.9 Using Low-ESR Capacitors
- 8.2.3 Application Curve
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2 Typical Application
Figure 36. Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
1. A 100-kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 37. Stereo Class-D Amplifier With PBTL Output and Single-Ended Input