ZHCSEE7 November 2015 TMP175-Q1 , TMP75-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7 Detailed Description
7.1 Overview
The TMP175-Q1 and TMP75-Q1 devices are digital temperature sensors that are optimal for thermal management and thermal protection applications. The TMP175-Q1 and TMP75-Q1 are two-wire, SMBus, and I2C interface compatible. The devices are specified over a temperature range of –40°C to +125°C. The Functional Block Diagram section shows the internal block diagram of the TMP175-Q1 and TMP75-Q1 devices.
The temperature sensor in the TMP175-Q1 and TMP75-Q1 devices is the chip itself. Thermal paths run through the package leads as well as the plastic package. The package leads provide the primary thermal path because of the lower thermal resistance of the metal.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only Temperature register. The Temperature register of the TMP175-Q1 or TMP75-Q1 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data and are listed in Table 6 and Table 7. The first 12 bits are used to indicate temperature with all remaining bits equal to zero. The data format for temperature is listed in Table 1. Negative numbers are represented in binary twos complement format. Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete.
The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature register are used with the unused least significant bits (LSBs) set to zero.
Table 1. Temperature Data Format
| TEMPERATURE (°C) |
DIGITAL OUTPUT | |
|---|---|---|
| BINARY | HEX | |
| 128 | 0111 1111 1111 | 7FF |
| 127.9375 | 0111 1111 1111 | 7FF |
| 100 | 0110 0100 0000 | 640 |
| 80 | 0101 0000 0000 | 500 |
| 75 | 0100 1011 0000 | 4B0 |
| 50 | 0011 0010 0000 | 320 |
| 25 | 0001 1001 0000 | 190 |
| 0.25 | 0000 0000 0100 | 004 |
| 0 | 0000 0000 0000 | 000 |
| –0.25 | 1111 1111 1100 | FFC |
| –25 | 1110 0111 0000 | E70 |
| –55 | 1100 1001 0000 | C90 |
7.3.2 Serial Interface
The TMP175-Q1 and TMP75-Q1 operate only as slave devices on the SMBus, two-wire, and I2C interface-compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP175-Q1 and TMP75-Q1 support the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38-MHz) modes. All data bytes are transmitted MSB first.
7.3.2.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.
To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted as a control signal.
When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high when SCL is high.
7.3.2.2 Serial Bus Address
To communicate with the TMP175-Q1 and TMP75-Q1, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation.
The TMP175-Q1 features three address pins to allow up to 27 devices to be addressed on a single bus interface. Table 2 describes the pin logic levels used to properly connect up to 27 devices. A 1 indicates that the pin is connected to the supply (VCC) and a 0 indicates that the pin is connected to GND; float indicates that the pin is left unconnected. The state of the A0, A1, and A2 pins is sampled on every bus communication and must be set prior to any activity on the interface.
Table 2. Address Pins and Slave Addresses for the TMP175-Q1
| A2 | A1 | A0 | SLAVE ADDRESS |
|---|---|---|---|
| 0 | 0 | 0 | 1001000 |
| 0 | 0 | 1 | 1001001 |
| 0 | 1 | 0 | 1001010 |
| 0 | 1 | 1 | 1001011 |
| 1 | 0 | 0 | 1001100 |
| 1 | 0 | 1 | 1001101 |
| 1 | 1 | 0 | 1001110 |
| 1 | 1 | 1 | 1001111 |
| Float | 0 | 0 | 1110000 |
| Float | 0 | Float | 1110001 |
| Float | 0 | 1 | 1110010 |
| Float | 1 | 0 | 1110011 |
| Float | 1 | Float | 1110100 |
| Float | 1 | 1 | 1110101 |
| Float | Float | 0 | 1110110 |
| Float | Float | 1 | 1110111 |
| 0 | Float | 0 | 0101000 |
| 0 | Float | 1 | 0101001 |
| 1 | Float | 0 | 0101010 |
| 1 | Float | 1 | 0101011 |
| 0 | 0 | Float | 0101100 |
| 0 | 1 | Float | 0101101 |
| 1 | 0 | Float | 0101110 |
| 1 | 1 | Float | 0101111 |
| 0 | Float | Float | 0110101 |
| 1 | Float | Float | 0110110 |
| Float | Float | Float | 0110111 |
The TMP75-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 3. The address pins of the TMP175-Q1 and TMP75-Q1 are read after reset, at start of communication, or in response to a two-wire address acquire request. After the state of the pins are read, the address is latched to minimize power dissipation associated with detection.
Table 3. Address Pins and Slave Addresses for the TMP75-Q1
| A2 | A1 | A0 | SLAVE ADDRESS |
|---|---|---|---|
| 0 | 0 | 0 | 1001000 |
| 0 | 0 | 1 | 1001001 |
| 0 | 1 | 0 | 1001010 |
| 0 | 1 | 1 | 1001011 |
| 1 | 0 | 0 | 1001100 |
| 1 | 0 | 1 | 1001101 |
| 1 | 1 | 0 | 1001110 |
| 1 | 1 | 1 | 1001111 |
7.3.2.3 Writing and Reading to the TMP175-Q1 and TMP75-Q1
Accessing a particular register on the TMP175-Q1 and TMP75-Q1 devices is accomplished by writing the appropriate value to the Pointer register. The value for the Pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP175-Q1 and TMP75-Q1 requires a value for the Pointer register (see Figure 7).
When reading from the TMP175-Q1 and TMP75-Q1 devices, the last value stored in the Pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command; see Figure 9 for details of this sequence. If repeated reads from the same register are desired, the Pointer register bytes do not have to be continually sent because the TMP175-Q1 and TMP75-Q1 remember the Pointer register value until it is changed by the next write operation.
Register bytes are sent MSB first, followed by the LSB.
7.3.2.4 Slave Mode Operations
The TMP175-Q1 and TMP75-Q1 can operate as a slave receiver or slave transmitter.
7.3.2.4.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP175-Q1 or TMP75-Q1 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer register. The TMP175-Q1 or TMP75-Q1 then acknowledges reception of the Pointer register byte. The next byte or bytes are written to the register addressed by the Pointer register. The TMP175-Q1 and TMP75-Q1 acknowledge reception of each data byte. The master can terminate data transfer by generating a START or STOP condition.
7.3.2.4.2 Slave Transmitter Mode
The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a Not-Acknowledge bit on reception of any data byte, or by generating a START or STOP condition.
7.3.2.5 SMBus Alert Function
The TMP175-Q1 and TMP75-Q1 support the SMBus alert function. When the TMP75-Q1 and TMP175-Q1 are operating in interrupt mode (TM = 1), the ALERT pin of the TMP75-Q1 or TMP175-Q1 can be connected as an SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP75-Q1 or TMP175-Q1 is active, the devices acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit is high if the temperature is greater than or equal to THIGH. This bit is low if the temperature is less than TLOW; see Figure 10 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device clears its ALERT status. If the TMP75-Q1 or TMP175-Q1 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP75-Q1 or TMP175-Q1 loses the arbitration, its ALERT pin remains active.
7.3.2.6 General Call
The TMP175-Q1 and TMP75-Q1 respond to a two-wire, general-call address (0000000) if the eighth bit is 0. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins, but do not reset. If the second byte is 00000110, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins and resets their internal registers to their power-up values.
7.3.2.7 High-Speed Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP175-Q1 and TMP75-Q1 devices do not acknowledge this byte, but do switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP175-Q1 and TMP75-Q1 switch the input and output filter back to fast-mode operation.
7.3.2.8 Time-out Function
The TMP175-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START and STOP condition. The TMP175-Q1 releases the bus if it is pulled low and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL operating frequency.
7.3.3 Timing Diagrams
The TMP175-Q1 and TMP75-Q1 devices are two-wire, SMBus, and I2C interface compatible. Figure 6 to Figure 10 describe the various operations on the TMP175-Q1. The following list provides bus definitions. Parameters for Figure 6 are defined in the Timing Requirements table.
Bus Idle: Both the SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge bit on the last byte that is transmitted by the slave.
7.3.3.1 Two-Wire Timing Diagrams
Figure 6. Two-Wire Timing Diagram
Figure 7. Two-Wire Timing Diagram for the TMP75-Q1 Write Word Format
Figure 8. Two-Wire Timing Diagram for the TMP175-Q1 Write Word Format
7.4 Device Functional Modes
7.4.1 Shutdown Mode (SD)
The shutdown mode of the TMP175-Q1 and TMP75-Q1 devices lets the user save maximum power by shutting down all device circuitry other than the serial interface, thus reducing current consumption to typically less than 0.1 μA. Shutdown mode is enabled when the SD bit is 1; the device shuts down when the current conversion is completed. When SD is equal to 0, the device maintains a continuous conversion state.
7.4.2 One-Shot (OS)
The TMP175-Q1 and TMP75-Q1 feature a one-shot temperature measurement mode. When the device is in shutdown mode, writing 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This feature is useful to reduce power consumption in the TMP175-Q1 and TMP75-Q1 when continuous temperature monitoring is not required. When the configuration register is read, OS always reads zero.
7.4.3 Thermostat Mode (TM)
The thermostat mode bit of the TMP175-Q1 and TMP75-Q1 indicates to the device whether to operate in comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section.
7.4.3.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the T(HIGH) register and remains active until the temperature falls below the value in the T(LOW) register. For more information on the comparator mode, see the High- and Low-Limit Registers section.
7.4.3.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below the T(LOW) registers. The ALERT pin is cleared when the host controller reads the Temperature register. For more information on the interrupt mode, see the High- and Low-Limit Registers section.
7.5 Programming
7.5.1 Pointer Register
Figure 11 shows the internal register structure of the TMP175-Q1 and TMP75-Q1. The 8-bit Pointer register of the devices is used to address a given data register. The Pointer register uses the two LSBs to identify which of the data registers must respond to a read or write command. Table 4 identifies the bits of the Pointer register byte. Table 5 describes the pointer address of the registers available in the TMP175-Q1 and TMP75-Q1. The power-up reset value of P1/P0 is 00.
Figure 11. Internal Register Structure of the TMP175-Q1 and TMP75-Q1
Table 4. Pointer Register Byte (pointer = N/A) [reset = 00h]
| P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | Register Bits | |
Table 5. Pointer Addresses of the TMP175-Q1 and TMP75-Q1
| P1 | P0 | TYPE | REGISTER |
|---|---|---|---|
| 0 | 0 | R only, default | Temperature register |
| 0 | 1 | R/W | Configuration register |
| 1 | 0 | R/W | TLOW register |
| 1 | 1 | R/W | THIGH register |
7.5.2 Temperature Register
The Temperature register of the TMP175-Q1 or TMP75-Q1 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data and are described in Table 6 and Table 7. Byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. Following the power-up or reset value, the Temperature register reads 0°C until the first conversion is complete.
Table 6. Byte 1 of the Temperature Register
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| T11 | T10 | T9 | T8 | T7 | T6 | T5 | T4 |
Table 7. Byte 2 of the Temperature Register
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| T3 | T2 | T1 | T0 | 0 | 0 | 0 | 0 |
7.5.3 Configuration Register
The Configuration register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read and write operations are performed MSB first. The format of the Configuration register for the TMP175-Q1 and TMP75-Q1 is shown in Table 8, followed by a breakdown of the register bits. The power-up or reset value of the Configuration register are all bits equal to 0.
Table 8. Configuration Register Format
| BYTE | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|
| 1 | OS | R1 | R0 | F1 | F0 | POL | TM | SD |
7.5.3.1 Polarity (POL)
The Polarity bit of the TMP175-Q1 lets the user adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default), the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes active high and the state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is shown in Figure 12.
Figure 12. Output Transfer Function Diagrams
7.5.3.2 Fault Queue (F1/F0)
A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW registers. Additionally, the number of fault conditions required to generate an alert can be programmed using the fault queue. The fault queue is provided to prevent a false alert resulting from environmental noise. The fault queue requires consecutive fault measurements in order to trigger the Alert function. Table 9 defines the number of measured faults that can be programmed to trigger an Alert condition in the device. For the THIGH and TLOW register format and byte order, see the High- and Low-Limit Registers section.
Table 9. Fault Settings of the TMP175-Q1 and TMP75-Q1
| F1 | F0 | CONSECUTIVE FAULTS |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 2 |
| 1 | 0 | 4 |
| 1 | 1 | 6 |
7.5.3.3 Converter Resolution (R1/R0)
The Converter Resolution bits control the resolution of the internal analog-to-digital (ADC) converter. This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 10 identifies the resolution bits and the relationship between resolution and conversion time.
Table 10. Resolution of the TMP175-Q1 and TMP75-Q1
| R1 | R0 | RESOLUTION | CONVERSION TIME (Typical) |
|---|---|---|---|
| 0 | 0 | 9 bits (0.5°C) | 27.5 ms |
| 0 | 1 | 10 bits (0.25°C) | 55 ms |
| 1 | 0 | 11 bits (0.125°C) | 110 ms |
| 1 | 1 | 12 bits (0.0625°C) | 220 ms |
7.5.4 High- and Low-Limit Registers
In comparator mode (TM = 0), the ALERT pin of the TMP175-Q1 and TMP75-Q1 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of faults.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also cleared if the device is placed in shutdown mode. When cleared, the ALERT pin only becomes active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and remains active until cleared by a read operation of any register or a successful response to the SMBus alert response address. When the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General-Call Reset command. This action also clears the state of the internal registers in the device, returning the device to comparator mode (TM = 0).
Both operational modes are represented in Figure 12. Table 11, Table 12, Table 13, and Table 14 describe the format for the THIGH and TLOW registers. The most significant byte is sent first, followed by the least significant byte. Power-up reset values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as for the Temperature register.
Table 11. Byte 1 of the THIGH Register
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| H11 | H10 | H9 | H8 | H7 | H6 | H5 | H4 |
Table 12. Byte 2 of the THIGH Register
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| H3 | H2 | H1 | H0 | 0 | 0 | 0 | 0 |
Table 13. Byte 1 of the TLOW Register
| BYTE | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|
| 1 | L11 | L10 | L9 | L8 | L7 | L6 | L5 | L4 |
Table 14. Byte 2 of the TLOW Register
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| L3 | L2 | L1 | L0 | 0 | 0 | 0 | 0 |
All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the Alert function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the Alert output even if the converter is configured for 9-bit resolution.