ZHCSIX4I August 2007 – June 2024 TMP102
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
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6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3 Feature Description
- 6.4 Device Functional Modes
- 6.5 Programming
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
6.3.11 Timing Diagrams
The TMP102 device is two-wire, SMBus, and I2C-interface compatible. Figure 6-1, Figure 6-2, Figure 6-3, and Figure 6-4 list the various operations on the TMP102 device. Parameters for Figure 6-1 are defined in the Timing Requirements table. The bus definitions are defined as follows:
- AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a controller receive, the termination of the data transfer can be signaled by the controller generating a not-acknowledge (1) on the last byte that has been transmitted by the target.
- Bus IdleBoth SDA and SCL lines remain high.
- Data TransferThe number of data bytes transferred between a START and a STOP condition is not limited and is determined by the controller device. The TMP102 device can also be used for single byte updates. To update only the MS byte, terminate the communication by issuing a START or STOP communication on the bus.
- Start Data TransferA change in the state of the SDA line, from high to low, when the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition.
- Stop Data TransferA change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Figure 6-1 Two-Wire Timing Diagram
Figure 6-2 Two-Wire Timing Diagram for Write Word Format
Figure 6-3 Two-Wire Timing Diagram for Read Word Format
Figure 6-4 Timing Diagram for SMBus Alert