| SUPPLY |
| IQ |
Quiescent current into VIN pin |
Not switching |
| 35 |
| uA |
| ISD |
Shutdown current into VIN pin |
EN = 0 V |
| 0.1 |
2 |
µA |
| VUVLO |
Under voltage lock out |
VIN falling |
| 2.3 |
2.45 |
V |
| Under voltage lock out hysteresis |
| | 100 |
| mV |
| TJSD |
Thermal shutdown |
Junction temperature rising |
| 150 |
| °C |
| Junction temperature falling |
| 130 |
|
| LOGIC INTERFACE |
| VIH |
High-level threshold at EN pin |
2.5 V ≤ VIN ≤ 5.5 V |
| 0.95 |
1.2 |
V |
| VIL |
Low-level threshold at EN pin |
2.5 V ≤ VIN ≤ 5.5 V |
0.4 |
0.85 |
| V |
| tSS |
Soft startup time |
TLV62569DBV |
| 800 |
| µs |
| TLV62569PDDC, TLV62569DRL, TLV62569PDRL |
| 900 |
|
| VPG |
Power good threshold |
VFB rising, referenced to VFB nominal |
| 95% |
| |
| VFB falling, referenced to VFB nominal |
| 90% |
| |
| VPG,OL |
Power good low-level output voltage |
ISINK = 1 mA |
| | 0.4 |
V |
| IPG,LKG |
Input leakage current into PG pin |
VPG = 5.0 V |
| 0.01 |
| µA |
| tPG,DLY |
Power good delay time |
VFB falling |
| 40 |
| µs |
| OUTPUT |
| VFB |
Feedback regulation voltage |
| 0.588 |
0.6 |
0.612 |
V |
| RDS(on) |
High-side FET on resistance |
| | 100 |
| mΩ |
| Low-side FET on resistance |
| | 60 |
|
| ILIM |
High-side FET current limit |
TLV62569DBV, TLV62569PDDC |
3 |
| | A |
| TLV62569DRL, TLV62569PDRL |
2.5 |
| |
| fSW |
Switching frequency |
VOUT = 2.5 V |
| 1.5 |
| MHz |