SLAS653C February 2010 – February 2017 TLV320AIC3120
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Device Comparison
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 Power Dissipation Ratings
- 5.7 I2S, LJF, and RJF Timing in Master Mode
- 5.8 I2S, LJF, and RJF Timing in Slave Mode
- 5.9 DSP Timing in Master Mode
- 5.10 DSP Timing in Slave Mode
- 5.11 I2C Interface Timing
- 5.12 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Power-Supply Sequence
- 7.3.2 Reset
- 7.3.3 Device Start-Up Lockout Times
- 7.3.4 PLL Start-Up
- 7.3.5 Power-Stage Reset
- 7.3.6 Software Power Down
- 7.3.7 Audio Analog I/O
- 7.3.8 miniDSP
- 7.3.9 Digital Processing Low-Power Modes
- 7.3.10
Audio ADC and Analog Inputs
- 7.3.10.1 MICBIAS and Microphone Preamplifier
- 7.3.10.2 Automatic Gain Control (AGC)
- 7.3.10.3 Delta-Sigma ADC
- 7.3.10.4
ADC Decimation Filtering and Signal Processing
- 7.3.10.4.1 ADC Processing Blocks
- 7.3.10.4.2
ADC Processing Blocks - Signal Chain Details
- 7.3.10.4.2.1 First-Order IIR, AGC, Filter A
- 7.3.10.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
- 7.3.10.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
- 7.3.10.4.2.4 First-Order IIR, AGC, Filter B
- 7.3.10.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B
- 7.3.10.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
- 7.3.10.4.2.7 First-Order IIR, AGC, Filter C
- 7.3.10.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C
- 7.3.10.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
- 7.3.10.4.3 User-Programmable Filters
- 7.3.10.4.4 ADC Digital Decimation Filter Characteristics
- 7.3.10.4.5 ADC Data Interface
- 7.3.10.5 Updating ADC Digital Filter Coefficients During Record
- 7.3.10.6 Digital Microphone Function
- 7.3.10.7 DC Measurement
- 7.3.10.8 ADC Setup
- 7.3.11 Example Register Setup to Record Analog Data Through ADC to Digital Out
- 7.3.12
Audio DAC and Audio Analog Outputs
- 7.3.12.1
DAC
- 7.3.12.1.1 DAC Processing Blocks
- 7.3.12.1.2
DAC Processing Blocks — Signal Chain Details
- 7.3.12.1.2.1 Three Biquads, Filter A
- 7.3.12.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B
- 7.3.12.1.2.3 Six Biquads, First-Order IIR, Filter A or B
- 7.3.12.1.2.4 IIR, Filter B or C
- 7.3.12.1.2.5 Four Biquads, DRC, Filter B
- 7.3.12.1.2.6 Four Biquads, Filter B
- 7.3.12.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C
- 7.3.12.1.2.8 Four Biquads, First-Order IIR, Filter C
- 7.3.12.1.2.9 Five Biquads, DRC, Beep Generator, Filter A
- 7.3.12.1.3 DAC User-Programmable Filters
- 7.3.12.1.4 DAC Interpolation Filter Characteristics
- 7.3.12.2 DAC Digital-Volume Control
- 7.3.12.3 Volume Control Pin
- 7.3.12.4 Dynamic Range Compression
- 7.3.12.5 Headset Detection
- 7.3.12.6 Interrupts
- 7.3.12.7 Key-Click Functionality With Beep Generator (PRB_P25)
- 7.3.12.8 Programming DAC Digital Filter Coefficients
- 7.3.12.9 Updating DAC Digital Filter Coefficients During PLAY
- 7.3.12.10 Digital Mixing and Routing
- 7.3.12.11 Analog Audio Routing
- 7.3.12.12 Analog Outputs
- 7.3.12.13 Audio-Output Stage-Power Configurations
- 7.3.12.14 DAC Setup
- 7.3.12.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
- 7.3.12.1
DAC
- 7.3.13 CLOCK Generation and PLL
- 7.3.14 Timer
- 7.3.15 Digital Audio and Control Interface
- 7.4
Register Map
- 7.4.1 TLV320AIC3120 Register Map
- 7.4.2
Registers
- 7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
- 7.4.2.2 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-Related Programmability
- 7.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
- 7.4.2.4 Control Registers, Page 4: ADC Digital Filter Coefficients
- 7.4.2.5 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
- 7.4.2.6 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
- 7.4.2.7 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
- 7.4.2.8 Control Registers, Page 10: DAC Programmable Coefficients RAM Buffer A (129:191)
- 7.4.2.9 Control Registers, Page 11: DAC Programmable Coefficients RAM Buffer A (193:255)
- 7.4.2.10 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
- 7.4.2.11 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
- 7.4.2.12 Control Registers, Page 14: DAC Programmable Coefficients RAM Buffer B (129:191)
- 7.4.2.13 Control Registers, Page 15: DAC Programmable Coefficients RAM Buffer B (193:255)
- 7.4.2.14 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
- 7.4.2.15 Control Registers, Pages 33-43: ADC DSP Engine Instruction RAM (32:63) Through (352:383)
- 7.4.2.16 Control Registers, Page 64: DAC DSP Engine Instruction RAM (0:31)
- 7.4.2.17 Control Registers, Pages 65 to 95: DAC DSP Engine Instruction RAM (32:63) Through (992:1023)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical Packaging and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
4 Pin Configuration and Functions
4.1 Pin Attributes
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AVDD | 17 | - | Analog power supply |
| AVSS | 16 | - | Analog ground |
| BCLK | 7 | I/O | Audio serial bit clock |
| DIN | 5 | I | Audio serial data input |
| DOUT | 4 | O | Audio serial data output |
| DVDD | 3 | - | Digital power – digital core |
| DVSS | 18 | - | Digital ground |
| GPIO1 | 32 | I/O | General-purpose input and output pin and multifunction pin |
| HPOUT | 27 | O | Mono headphone and line driver output |
| NC | 30 | O | No connection |
| HPVDD | 28 | - | Headphone/line driver and PLL power |
| HPVSS | 29 | - | Headphone/line driver and PLL ground |
| IOVDD | 2 | - | Interface power |
| IOVSS | 1 | - | Interface ground |
| MCLK | 8 | I | External master clock |
| MICBIAS | 12 | O | |
| MIC1LM | 15 | I | Microphone/line input routed to M or P input mixer |
| MIC1LP | 13 | I | Microphone/line input routed to P input mixer and left output mixer |
| MIC1RP | 14 | I | Microphone/line input routed to P input mixer and left/right output mixer |
| RESET | 31 | I | Device reset |
| SCL | 10 | I/O | I2C control bus clock input |
| SDA | 9 | I/O | I2C control-bus data input |
| SPKM | 19, 23 | I/O | Cass-D speaker driver inverting output |
| SPKP | 22, 26 | - | Class-D speaker driver noninverting output |
| SPKVDD | 21, 24 | - | Class-D speaker driver power supply |
| SPKVSS | 20, 25 | - | Class-D speaker driver power-supply ground |
| VOL/MICDET | 11 | I | Volume control or microphone detection |
| WCLK | 6 | I/O | Audio serial word clock |