SLAS647C December 2009 – May 2016 TLV320AIC3110
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Device Comparison
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 Power Dissipation Ratings
- 5.7 I2S, LJF, and RJF Timing in Master Mode
- 5.8 I2S, LJF, and RJF Timing in Slave Mode
- 5.9 DSP Timing in Master Mode
- 5.10 DSP Timing in Slave Mode
- 5.11 I2C Interface Timing
- 5.12 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Power-Supply Sequence
- 7.3.2 Reset
- 7.3.3 Device Start-Up Lockout Times
- 7.3.4 PLL Start-Up
- 7.3.5 Power-Stage Reset
- 7.3.6 Software Power Down
- 7.3.7 Audio Analog I/O
- 7.3.8
Digital Processing Low-Power Modes
- 7.3.8.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V
- 7.3.8.2 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V
- 7.3.8.3 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 7.3.8.4 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 7.3.8.5 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 7.3.8.6 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 7.3.8.7 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
- 7.3.8.8 DAC Playback on Line Out (10 k-? load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
- 7.3.9
Audio ADC and Analog Inputs
- 7.3.9.1 MICBIAS and Microphone Preamplifier
- 7.3.9.2 Automatic Gain Control (AGC)
- 7.3.9.3 Delta-Sigma ADC
- 7.3.9.4
ADC Decimation Filtering and Signal Processing
- 7.3.9.4.1 ADC Processing Blocks
- 7.3.9.4.2
ADC Processing Blocks - Signal Chain Details
- 7.3.9.4.2.1 First-Order IIR, AGC, Filter A
- 7.3.9.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
- 7.3.9.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
- 7.3.9.4.2.4 First-Order IIR, AGC, Filter B
- 7.3.9.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B
- 7.3.9.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
- 7.3.9.4.2.7 First-Order IIR, AGC, Filter C
- 7.3.9.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C
- 7.3.9.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
- 7.3.9.4.3 User-Programmable Filters
- 7.3.9.4.4 ADC Digital Decimation Filter Characteristics
- 7.3.9.4.5 ADC Data Interface
- 7.3.9.5 Updating ADC Digital Filter Coefficients During Record
- 7.3.9.6 Digital Microphone Function
- 7.3.9.7 DC Measurement
- 7.3.10
Audio DAC and Audio Analog Outputs
- 7.3.10.1
DAC
- 7.3.10.1.1 DAC Processing Blocks
- 7.3.10.1.2
DAC Processing Blocks — Details
- 7.3.10.1.2.1 Three Biquads, Filter A
- 7.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B
- 7.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B
- 7.3.10.1.2.4 IIR, Filter B or C
- 7.3.10.1.2.5 Four Biquads, DRC, Filter B
- 7.3.10.1.2.6 Four Biquads, Filter B
- 7.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C
- 7.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C
- 7.3.10.1.2.9 Two Biquads, 3D, Filter A
- 7.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
- 7.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
- 7.3.10.1.3 DAC User-Programmable Filters
- 7.3.10.1.4 DAC Interpolation Filter Characteristics
- 7.3.10.2 DAC Digital-Volume Control
- 7.3.10.3 Volume Control Pin
- 7.3.10.4 Dynamic Range Compression
- 7.3.10.5 Headset Detection
- 7.3.10.6 Interrupts
- 7.3.10.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
- 7.3.10.8 Programming DAC Digital Filter Coefficients
- 7.3.10.9 Updating DAC Digital Filter Coefficients During PLAY
- 7.3.10.10 Digital Mixing and Routing
- 7.3.10.11 Analog Audio Routing
- 7.3.10.12 Analog Outputs
- 7.3.10.13 Audio-Output Stage-Power Configurations
- 7.3.10.14 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
- 7.3.10.1
DAC
- 7.3.11 CLOCK Generation and PLL
- 7.3.12 Timer
- 7.3.13 Digital Audio and Control Interface
- 7.4
Register Map
- 7.4.1 TLV320AIC3110 Register Map
- 7.4.2
Registers
- 7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
- 7.4.2.2 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-Related Programmability
- 7.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
- 7.4.2.4 Control Registers, Page 4: ADC Digital Filter Coefficients
- 7.4.2.5 Control Registers, Page 8: DAC Digital Filter Coefficients
- 7.4.2.6 Control Registers, Page 9: DAC Digital Filter Coefficients
- 7.4.2.7 Control Registers, Page 12: DAC Programmable Coefficients Buffer B (1:63)
- 7.4.2.8 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical Packaging and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
10 Layout
10.1 Layout Guidelines
PCB design is made considering the application and the review is specific for each system requirements. However, general considerations can optimize the system performance.
- The TLV320AIC3110 thermal pad must be connected to analog output driver ground using multiple VIAS to minimize impedance between the device and ground.
- Analog and digital grounds must be separated to prevent possible digital noise form affecting the analog performance of the board.
- The TLV320AIC3110 requires the decoupling capacitors to be placed as close as possible to the device power supply terminals.
10.2 Layout Example
Figure 10-1 Example PCB Layout