SLAS513C February 2007 – December 2014 TLV320AIC3105
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| AVDD to AVSS, DRVDD to DRVSS | –0.3 | 3.9 | V | |
| AVDD to DRVSS | –0.3 | 3.9 | V | |
| IOVDD to DVSS | –0.3 | 3.9 | V | |
| DVDD to DVSS | –0.3 | 2.5 | V | |
| AVDD to DRVDD | –0.1 | 0.1 | V | |
| Digital input voltage to DVSS | –0.3 | IOVDD + 0.3 | V | |
| Analog input voltage to AVSS | –0.3 | AVDD + 0.3 | V | |
| Operating temperature range | –40 | 85 | °C | |
| TJ Max | Junction temperature | 105 | °C | |
| Power dissipation | (TJ Max – TA)/ θJA | |||
| θJA | Thermal impedance | 44 | °C/W | |
| Tstg | Storage temperature range | –65 | 105 | °C |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| AVDD, DRVDD1/2(1) | Analog supply voltage | 2.7 | 3.3 | 3.6 | V |
| DVDD(1) | Digital core supply voltage | 1.525 | 1.8 | 1.95 | V |
| IOVDD(1) | Digital I/O supply voltage | 1.1 | 1.8 | 3.6 | V |
| VI | Analog full-scale 0-dB input voltage (DRVDD1 = 3.3 V) | 0.63 | VRMS | ||
| Stereo line output load resistance | 10 | kΩ | |||
| Stereo headphone output load resistance | 16 | Ω | |||
| Digital output load capacitance | 10 | pF | |||
| TA | Operating free-air temperature | –40 | 85 | °C |
| THERMAL METRIC(1) | TLV320AIC3105I | UNIT | |
|---|---|---|---|
| RHB | |||
| 32 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 31.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 22.3 | |
| RθJB | Junction-to-board thermal resistance | 5.9 | |
| ψJT | Junction-to-top characterization parameter | 0.3 | |
| ψJB | Junction-to-board characterization parameter | 5.9 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.2 | |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUDIO ADC | ||||||
| Input signal level (0 dB) | Single-ended input | 0.707 | VRMS | |||
| Signal-to-noise ratio(1)(2) | fS = 48 ksps, 0 dB PGA gain, inputs ac-shorted to ground, A-weighted | 80 | 92 | dB | ||
| Dynamic range(1)(2) | fS = 48 ksps; 0-dB PGA gain –60-dB full-scale, 1-kHz input signal | 93 | dB | |||
| THD | Total harmonic distortion | fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal | –89 | –75 | dB | |
| PSRR | Power-supply rejection ratio | 217-Hz signal applied to DRVDD | 55 | dB | ||
| 1-kHz signal applied to DRVDD | 44 | |||||
| Input channel separation | 1-kHz, –2 dB full-scale signal, MIC1L to MIC1R | –71 | dB | |||
| Gain error | fS = 48 ksps, 0 dB PGA gain, –2 dB full-scale 1-kHz input signal | 0.82 | dB | |||
| ADC programmable gain amplifier maximum gain | 1-kHz input tone | 59.5 | dB | |||
| ADC programmable gain amplifier step size | 0.5 | dB | ||||
| Input resistance | MIC1L/MIC1R inputs routed to single ADC Input multiplex attenuation = 0 dB | 20 | kΩ | |||
| MIC1L/MIC1R inputs routed to single ADC Input multiplex attenuation = 12 dB | 80 | |||||
| MIC2L/MIC2R inputs routed to single ADC Input multiplex attenuation = 0 dB | 20 | |||||
| MIC2L/MIC2R inputs routed to single ADC Input multiplex attenuation = 12 dB | 80 | |||||
| MIC3L/MIC3R inputs routed to single ADC Input multiplex attenuation = 0 dB | 20 | |||||
| MIC3L/MIC3R inputs routed to single ADC Input multiplex attenuation = 12 dB | 80 | |||||
| Input capacitance | MIC1/LINE1 inputs | 10 | pF | |||
| Input level control minimum attenuation setting | 0 | dB | ||||
| Input level control maximum attenuation setting | 12 | dB | ||||
| Input level control attenuation step size | 1.5 | dB | ||||
| ANALOG PASSTHROUGH MODE | ||||||
| Input-to-output switch resistance | MIC1/LIN1 to LINEOUT, Rds ON | 330 | Ω | |||
| MIC2/LIN2 to LINEOUT, Rds ON | 330 | |||||
| ADC DIGITAL DECIMATION FILTER, fS = 48 kHz | ||||||
| Filter gain from 0 to 0.39 fS | ±0.1 | dB | ||||
| Filter gain at 0.4125 fS | –0.25 | dB | ||||
| Filter gain at 0.45 fS | –3 | dB | ||||
| Filter gain at 0.5 fS | –17.5 | dB | ||||
| Filter gain from 0.55 fS to 64 fS | –75 | dB | ||||
| Filter group delay | 17/fS | s | ||||
| MICROPHONE BIAS | ||||||
| Bias voltage | Programmable setting = 2 V | 2 | V | |||
| Programmable setting = 2.5 V | 2.3 | 2.455 | 2.7 | |||
| Programmable setting = DRVDD | DRVDD –0.24 | |||||
| Current sourcing | Programmable setting = 2.5 V | 4 | mA | |||
| AUDIO DAC – DIFFERENTIAL LINE OUTPUT, LOAD = 10 kΩ | ||||||
| Full-scale output voltage | 0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 1.414 | VRMS | |||
| 4 | VPP | |||||
| SNR | Signal-to-noise ratio | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted |
90 | 102 | dB | |
| Dynamic range | –60-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted |
99 | dB | |||
| THD | Total harmonic distortion | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–95 | –75 | dB | |
| PSRR | Power-supply rejection ratio | 217-Hz signal applied to DRVDD, AVDD_DAC | 78 | dB | ||
| 1-kHz signal applied to DRVDD, AVDD_DAC | 80 | |||||
| DAC channel separation | 0-dB full-scale input signal, between left and right LINEOUT | 86 | dB | |||
| DAC interchannel gain mismatch | 1-kHz input, 0-dB gain | 0.1 | dB | |||
| DAC gain error | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–0.2 | dB | |||
| AUDIO DAC – SINGLE-ENDED LINE OUTPUT, LOAD = 10 kΩ | ||||||
| Full-scale output voltage | 0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V |
0.707 | VRMS | |||
| SNR | Signal-to-noise ratio | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted |
97 | dB | ||
| THD | Total harmonic distortion | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–84 | dB | ||
| DAC gain error | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
0.55 | dB | |||
| AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, LOAD = 16 Ω | ||||||
| Full-scale output voltage | 0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V |
0.707 | VRMS | |||
| SNR | Signal-to-noise ratio | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted |
96 | dB | ||
| No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, DAC current-boost mode |
97 | dB | ||||
| Dynamic range | –60-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted |
97 | dB | |||
| THD | Total harmonic distortion | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–71 | –65 | dB | |
| PSRR | Power-supply rejection ratio | 217-Hz signal applied to DRVDD, AVDD_DAC | 43 | dB | ||
| 1-kHz signal applied to DRVDD, AVDD_DAC | 41 | |||||
| DAC channel separation | 0-dB full-scale input signal, between left and right headphone out | 89 | dB | |||
| DAC gain error | 0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–0.85 | dB | |||
| AUDIO DAC – LINEOUT AND HEADPHONE OUT DRIVERS | ||||||
| Output common mode | First option | 1.35 | V | |||
| Second option | 1.5 | |||||
| Third option | 1.65 | |||||
| Fourth option | 1.8 | |||||
| Output volume control maximum setting | 9 | dB | ||||
| Output volume control step size | 1 | dB | ||||
| DAC DIGITAL INTERPOLATION – FILTER fS = 48 kHz | ||||||
| Pass band | 0 | 0.45 fS | Hz | |||
| Pass-band ripple | ±0.06 | dB | ||||
| Transition band | 0.45 fS | 0.55 fS | Hz | |||
| Stop band | 0.55 fS | 7.5 fS | Hz | |||
| Stop-band attenuation | 65 | dB | ||||
| Group delay | 21/fS | s | ||||
| STEREO HEADPHONE DRIVER – AC-COUPLED OUTPUT CONFIGURATION(3) | ||||||
| 0-dB full-scale output voltage | 0-dB gain to high-power outputs. Output common-mode voltage setting = 1.35 V | 0.707 | VRMS | |||
| Programmable output common-mode voltage (applicable to line outputs also) | First option | 1.35 | V | |||
| Second option | 1.5 | |||||
| Third option | 1.65 | |||||
| Fourth option | 1.8 | |||||
| Maximum programmable output level control gain | 9 | dB | ||||
| Programmable output level control gain step size | 1 | dB | ||||
| PO | Maximum output power | RL = 32 Ω | 15 | mW | ||
| RL = 16 Ω | 30 | |||||
| Signal-to-noise ratio(3) | A-weighted | 94 | dB | |||
| Total harmonic distortion | 1-kHz output, PO = 5 mW, RL = 32 Ω | –77 | dB% | |||
| 0.014 | ||||||
| 1-kHz output, PO = 10 mW, RL = 32 Ω | –76 | |||||
| 0.016 | ||||||
| 1-kHz output, PO = 10 mW, RL = 16 Ω | –73 | |||||
| 0.022 | ||||||
| 1-kHz output, PO = 20 mW, RL = 16 Ω | –71 | |||||
| 0.028 | ||||||
| Channel separation | 1-kHz, 0-dB input | 90 | dB | |||
| Power supply rejection ratio | 217 Hz, 100 mVpp on AVDD, DRVDD1/2 | 48 | dB | |||
| Mute attenuation | 1-kHz output | 107 | dB | |||
| DIGITAL I/O | ||||||
| VIL | Input low level | –0.3 | 0.3 IOVDD | V | ||
| VIH | Input high level | IOVDD > 1.6 V | 0.7 IOVDD | V | ||
| IOVDD ≤ 1.6 V | 1.1 | |||||
| VOL | Output low level | 0.1 IOVDD | V | |||
| VOH | Output high level | 0.8 IOVDD | V | |||
| CURRENT CONSUMPTION – DRVDD, IOVDD = AVDD_DAC = 3.3 V, DVDD = 1.8 V | ||||||
| IIN | IDRVDD + IAVDD_DAC | RESET held low | 0.1 | µA | ||
| IDVDD | 0.2 | |||||
| IDRVDD + IAVDD_DAC | Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal | 2.15 | mA | |||
| IDVDD | 0.48 | |||||
| IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal | 4.1 | mA | |||
| IDVDD | 0.62 | |||||
| IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal | 4.31 | mA | |||
| IDVDD | 2.45 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to Lineout, analog mixer bypassed, fS = 48 ksps, I2S slave |
3.5 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to Lineout, fS = 48 ksps, I2S slave, no signal |
4.9 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signal |
6.7 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo Linein to stereo Lineout, no signal | 3.11 | mA | |||
| IDVDD | 0 | |||||
| IDRVDD + IAVDD_DAC | Extra power when PLL enabled | 1.4 | mA | |||
| IDVDD | 0.9 | |||||
| IDRVDD + IAVDD_DAC | All blocks powered down. Headset detection enabled, headset not inserted. | 28 | µA | |||
| IDVDD | 2 | |||||
| IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | ||||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| I2S/LJF/RJF TIMING IN MASTER MODE | ||||||
| td(WS) | ADWS/WCLK delay time | 50 | 15 | ns | ||
| td(DO-WS) | ADWS/WCLK to DOUT delay time | 50 | 20 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 30 | 10 | ns | ||
| tf | Fall time | 30 | 10 | ns | ||
| DSP TIMING IN MASTER MODE | ||||||
| td(WS) | ADWS/WCLK delay time | 50 | 15 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 30 | 10 | ns | ||
| tf | Fall time | 30 | 10 | ns | ||
| I2S/LJF/RJF TIMING IN SLAVE MODE | ||||||
| tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
| ts(WS) | ADWS/WCLK setup time | 10 | 6 | ns | ||
| th(WS) | ADWS/WCLK hold time | 10 | 6 | ns | ||
| td(DO-WS) | ADWS/WCLK to DOUT delay time (for LJF Mode only) | 50 | 35 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 8 | 4 | ns | ||
| tf | Fall time | 8 | 4 | ns | ||
| DSP TIMING IN MASTER MODE | ||||||
| tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
| tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
| ts(WS) | ADWS/WCLK setup time | 10 | 8 | ns | ||
| th(WS) | ADWS/WCLK hold time | 10 | 8 | ns | ||
| td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
| ts(DI) | DIN setup time | 10 | 6 | ns | ||
| th(DI) | DIN hold time | 10 | 6 | ns | ||
| tr | Rise time | 8 | 4 | ns | ||
| tf | Fall time | 8 | 4 | ns | ||
Figure 1. I2S/LJF/RJF Timing in Master Mode
Figure 2. DSP Timing in Master Mode
Figure 3. I2S/LJF/RJF Timing in Slave Mode
Figure 4. DSP Timing in Slave Mode






