ZHCSK11A July 2019 – October 2019 TLV320ADC5140
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The device integrates an ultra-low noise front-end PGA with 120-dB dynamic range performance with a low-noise, low-distortion, multibit delta-sigma (ΔΣ) ADC with a 108-dB dynamic range. The dynamic range enhancer (DRE) is a digitally assisted algorithm to boost the overall channel performance. The DRE monitors the incoming signal amplitude and accordingly adjusts the internal PGA gain automatically. The DRE achieves a complete-channel dynamic range as high as 120 dB. At a system level, the DRE scheme enables far-field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud environments.
This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize any audible artifacts that may occur resulting from dynamic gain modulation. Additionally, the host can configure the target signal threshold level at which DRE is triggered by setting the appropriate value for the DRE_LVL[3:0], P0_R109[7:4] register bits. The DRE_LVL default level is set to –54 dB and TI recommends setting the DRE_LVL value lower than –30 dB to maximize the benefit of the DRE in real-world applications and to minimize any audible artifacts. Table 44 lists the DRE_LVL configuration settings.
| P0_R109_D[7:4] : DRE_LVL[3:0] | DRE TRIGGER THRESHOLD LEVEL |
|---|---|
| 0000 | The DRE trigger threshold is the –12-dB input signal level |
| 0001 | The DRE trigger threshold is the –18-dB input signal level |
| 0010 | The DRE trigger threshold is the –24-dB input signal level |
| … | … |
| 0111 (default) | The DRE trigger threshold is the –54-dB input signal level |
| … | … |
| 1001 | The DRE trigger threshold is the –66-dB input signal level |
| 1010 to 1111 | Reserved (do not use these settings) |
The DRE gain range can be dynamically modulated by using the DRE_MAXGAIN[3:0, P0_R109[3:0] register bits. The DRE_MAXGAIN default value is set to 24 dB, and the DRE_MAXGAIN value is recommended to be set lower than 24 dB to maximize the benefit of the DRE in real-world applications and to minimize any audible artifacts. Table 45 lists the DRE_MAXGAIN configuration settings.
| P0_R109_D[3:0] : DRE_MAXGAIN[3:0] | DRE MAXIMUM GAIN ALLOWED |
|---|---|
| 0000 | The DRE maximum gain allowed is 2 dB |
| 0001 | The DRE maximum gain allowed is 4 dB |
| 0010 | The DRE maximum gain allowed is 6 dB |
| … | … |
| 1011 (default) | The DRE maximum gain allowed is 24 dB |
| … | … |
| 1110 | The DRE maximum gain allowed is 30 dB |
| 1111 | Reserved (do not use this setting) |
The DRE scheme is only supported for analog microphone recording channels with an AC-coupled input for best dynamic range performance. The DRE scheme can be independently enabled or disabled for each channel using the CH1_DREEN (P0_R60_D0), CH2_DREEN (P0_R65_D0), CH3_DREEN (P0_R70_D0), and CH4_DREEN (P0_R75_D0) register bits. For a DC-coupled input, the DRE scheme can be used with limited DRE_MAXGAIN depending on the DC differential input common-mode offset.
Enabling the DRE for processing increases the power consumption of the device because of increased signal processing. Therefore, disable the DRE for low-power critical applications. Furthermore, the DRE is not supported for output sample rates greater than 192 kHz.