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ZHCSK11A July 2019 – October 2019 TLV320ADC5140

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

RTW|24

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

at T_A = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN = 1-kHz sinusoidal signal, f_S = 48 kHz, 32-bit audio data, BCLK = 256 × f_S, TDM slave mode, PLL on (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ADC CONFIGURATION
	AC input impedance	Input pins INxP or INxM, 2.5-kΩ input impedance selection		2.5		kΩ
		Input pins INxP or INxM, 10-kΩ input impedance selection		10
		Input pins INxP or INxM, 20-kΩ input impednace selection		20
	Channel gain range	Programmable range with 1-dB steps	0		42	dB
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
	Differential input full-scale AC signal voltage	AC-coupled input		2		V_RMS
	Single-ended input full-scale AC signal voltage	AC-coupled input		1		V_RMS
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection	112	119		dB
		IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		116
		IN1 differential input selected and AC signal shorted to ground, DRE disabled, 10-kΩ input impedance selection, 0-dB channel gain	102	107
		IN1 differential input selected and AC signal shorted to ground, DRE disabled, 10-kΩ input impedance selection, 12-dB channel gain		102
DR	Dynamic range, A-weighted⁽²⁾	IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection		120		dB
		IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		117
		IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 10-kΩ input impedance selection, 0-dB channel gain		108
		IN1 differential input selected and –72-dB full-scale AC signal input, DRE disabled, 10-kΩ input impedance selection, 12-dB channel gain		103
THD+N	Total harmonic distortion⁽²⁾⁽³⁾	IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection		–98	–80	dB
		IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		–98
		IN1 differential input selected and –1-dB full-scale AC signal input, DRE disabled, 10-kΩ input impedance selection, 0-dB channel gain		–98
		IN1 differential input selected and –13-dB full-scale AC signal input, DRE disabled, 10-kΩ input impedance selection, 12-dB channel gain		–95
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 1.8-V OPERATION
	Differential input full-scale AC signal voltage	AC-coupled Input		1		V_RMS
	Single-ended input full-scale AC signal voltage	AC-coupled Input		0.5		V_RMS
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection		112		dB
		IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		110
		IN1 differential input selected and AC signal shorted to ground, DRE disabled, 10-kΩ input impedance selection, 0-dB channel gain		100
DR	Dynamic range, A-weighted⁽²⁾	IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection		113		dB
		IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		111
		IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 0-dB channel gain		101
THD+N	Total harmonic distortion⁽²⁾⁽³⁾	IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection		–90		dB
		IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection		–90
		IN1 differential input selected and –2-dB full-scale AC signal Input, DRE disabled, 10-kΩ input impedance selection, 0 dB channel gain		–90
ADC OTHER PARAMETERS
	Digital volume control range	Programmable 0.5-dB steps	–100		27	dB
	Output data sample rate	Programmable	7.35		768	kHz
	Output data sample word length	Programmable	16		32	Bits
	Digital high-pass filter cutoff frequency	First-order IIR filter with programmable coefficients, –3-dB point (default setting)		12		Hz
	Interchannel isolation	–1-dB full-scale AC-signal input to non measurement channel		–124		dB
	Interchannel gain mismatch	–6-dB full-scale AC-signal input and 0-dB channel gain		0.1		dB
	Gain drift	0-dB channel gain, across temperature range 15°C to 35°C		–4.4		ppm/°C
	Interchannel phase mismatch	1-kHz sinusoidal signal		0.02		Degrees
	Phase drift	1-kHz sinusoidal signal, across temperature range 15°C to 35°C		0.0005		Degrees/°C
PSRR	Power-supply rejection ratio	100-mV_PP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain		102		dB
CMRR	Common-mode rejection ratio	Differential microphone input selected, 0-dB channel gain, 100-mV_PP, 1-kHz signal on both pins and measure level at output		60		dB
MICROPHONE BIAS
	MICBIAS noise	BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS		1.6		µV_RMS
	MICBIAS voltage	MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V		VREF		V
		MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V		VREF × 1.096
		Bypass to AVDD with 20-mA load		AVDD – 0.2
	MICBIAS current drive	MICBIAS voltage ≥ 2.5 V			20	mA
	MICBIAS current drive	MICBIAS voltage < 2.5 V			10	mA
	MICBIAS load regulation	MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load	0.1	0.6	1.8	%
	MICBIAS over current protection threshold		30			mA
DIGITAL I/O
V_IL	Low-level digital input logic voltage threshold	All digital pins except INxP_GPIx, SDA and SCL, IOVDD 1.8-V operation	–0.3		0.35 × IOVDD	V
V_IL	Low-level digital input logic voltage threshold	All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation	–0.3		0.8	V
V_IH	High-level digital input logic voltage threshold	All digital pins except INxP_GPIx, SDA and SCL, IOVDD 1.8-V operation	0.65 × IOVDD		IOVDD + 0.3	V
V_IH	High-level digital input logic voltage threshold	All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation	2		IOVDD + 0.3	V
V_OL	Low-level digital output voltage	All digital pins except INxM_GPOx, SDA and SCL, I_OL = –2 mA, IOVDD 1.8-V operation			0.45	V
V_OL	Low-level digital output voltage	All digital pins except INxM_GPOx, SDA and SCL, I_OL = –2 mA, IOVDD 3.3-V operation			0.4	V
V_OH	High-level digital output voltage	All digital pins except INxM_GPOx, SDA and SCL, I_OH = 2 mA, IOVDD 1.8-V operation	IOVDD – 0.45			V
V_OH	High-level digital output voltage	All digital pins except INxM_GPOx, SDA and SCL, I_OH = 2 mA, IOVDD 3.3-V operation	2.4			V
V_IL(I2C)	Low-level digital input logic voltage threshold	SDA and SCL	–0.5		0.3 x IOVDD	V
V_IH(I2C)	High-level digital input logic voltage threshold	SDA and SCL	0.7 x IOVDD		IOVDD + 0.5	V
V_OL1(I2C)	Low-level digital output voltage	SDA, I_OL(I2C) = –3 mA, IOVDD > 2 V			0.4	V
V_OL2(I2C)	Low-level digital output voltage	SDA, I_OL(I2C) = –2 mA, IOVDD ≤ 2 V			0.2 x IOVDD	V
I_OL(I2C)	Low-level digital output current	SDA, V_OL(I2C) = 0.4 V, standard-mode or fast-mode	3			mA
I_OL(I2C)	Low-level digital output current	SDA, V_OL(I2C) = 0.4 V, fast-mode plus	20			mA
I_IH	Input logic-high leakage for digital inputs	All digital pins except INxP_GPIx pins, input = IOVDD	–5	0.1	5	µA
I_IL	Input logic-low leakage for digital inputs	All digital pins except INxP_GPIx pins, input = 0 V	–5	0.1	5	µA
V_IL(GPIx)	Low-level digital input logic voltage threshold	All INxP_GPIx digital pins, AVDD 1.8-V operation	–0.3		0.35 × AVDD	V
V_IL(GPIx)	Low-level digital input logic voltage threshold	All INxP_GPIx digital pins, AVDD 3.3-V operation	–0.3		0.8	V
V_IH(GPIx)	High-level digital input logic voltage threshold	All INxP_GPIx digital pins, AVDD 1.8-V operation	0.65 × AVDD		AVDD + 0.3	V
V_IH(GPIx)	High-level digital input logic voltage threshold	All INxP_GPIx digital pins, AVDD 3.3-V operation	2		AVDD + 0.3	V
V_OL(GPOx)	Low-level digital output voltage	All INxM_GPOx digital pins, I_OL = –2 mA, AVDD 1.8-V operation			0.45	V
V_OL(GPOx)	Low-level digital output voltage	All INxM_GPOx digital pins, I_OL = –2 mA, AVDD 3.3-V operation			0.4	V
V_OH(GPOx)	High-level digital output voltage	All INxM_GPOx digital pins, I_OH = 2 mA, AVDD 1.8-V operation	AVDD – 0.45			V
V_OH(GPOx)	High-level digital output voltage	All INxM_GPOx digital pins, I_OH = 2 mA, AVDD 3.3-V operation	2.4			V
I_IH(GPIx)	Input logic-high leakage for digital inputs	All INxP_GPIx digital pins, input = AVDD	–5	0.1	5	µA
I_IL(GPIx)	Input logic-high leakage for digital inputs	All INxP_GPIx digital pins, input = 0 V	–5	0.1	5	µA
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
R_PD	Pulldown resistance for digital I/O pins when asserted on			20		kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
I_AVDD	Current consumption in hardware shutdown mode	SHDNZ = 0, AVDD = 3.3 V, internal AREG		0.5		µA
I_AVDD		SHDNZ = 0, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		0.5
I_IOVDD		SHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V		0.1
I_IOVDD		SHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V		0.1
I_AVDD	Current consumption in sleep mode (software shutdown mode)	All external clocks stopped, AVDD = 3.3 V, internal AREG		5		µA
I_AVDD		All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		5
I_IOVDD		All external clocks stopped, IOVDD = 3.3 V		0.1
I_IOVDD		All external clocks stopped, IOVDD = 1.8 V		0.1
I_AVDD	Current consumption with ADC 2-channel operating at f_S 48-kHz, PLL off, BCLK = 512 × f_S and DRE disable	AVDD = 3.3 V, internal AREG		11.3		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		10.7
I_IOVDD		IOVDD = 3.3 V		0.1
I_IOVDD		IOVDD = 1.8 V		0.05
I_AVDD	Current consumption with ADC 4-channel operating at f_S 16-kHz, PLL on, BCLK = 256 × f_S and DRE disable	AVDD = 3.3 V, internal AREG		19.7		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		18.6
I_IOVDD		IOVDD = 3.3 V		0.05
I_IOVDD		IOVDD = 1.8 V		0.02
I_AVDD	Current consumption with ADC 4-channel operating at f_S 48-kHz, PLL on, BCLK = 256 × f_S and DRE disable	AVDD = 3.3 V, internal AREG		21.3		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		20.2
I_IOVDD		IOVDD = 3.3 V		0.1
I_IOVDD		IOVDD = 1.8 V		0.05
I_AVDD	Current consumption with ADC 4-channel operating at f_S 48-kHz, PLL on, BCLK = 256 × f_S and DRE enable	AVDD = 3.3 V, internal AREG		23.6		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		22.3
I_IOVDD		IOVDD = 3.3 V		0.1
I_IOVDD		IOVDD = 1.8 V		0.05

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) For best distortion performance, use input AC-coupling capacitors with low-voltage-coefficient.