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SLAS553B November 2008 – August 2015 TLV320ADC3101

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機械數據 (封裝 | 引腳)

RGE|24
- QFND008AA

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
	AVDD to AVSS	–0.3	3.9	V
	IOVDD to DVSS	–0.3	3.9	V
	DVDD to DVSS	–0.3	2.5	V
	Digital input voltage to DVSS	–0.3	IOVDD + 0.3	V
	Analog input voltage to AVSS	–0.3	AVDD + 0.3	V
	Operating temperature	–40	85	°C
T_J Max	Junction temperature		105	°C
	Power dissipation	(T_J Max – T_A) / θ_JA		W
T_stg	Storage temperature	–65	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) ESD complacence tested to EIA / JESD22-A114-B and passed.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD⁽¹⁾	Analog supply voltage	2.6	3.3	3.6	V
DVDD⁽¹⁾	Digital core supply voltage	1.65	1.8	1.95	V
IOVDD⁽¹⁾	Digital I/O supply voltage	1.1	1.8	3.6	V
V_I	Analog full-scale 0-dB input voltage (AVDD = 3.3 V)		0.707		Vrms
	Digital output load capacitance		10		pF
T_A	Operating free-air temperature	–40		85	°C

(1) Analog voltage values are with respect to AVSS; digital voltage values are with respect to DVSS.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV320ADC3101	UNIT
		RGE (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	33.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	34.1	°C/W
R_θJB	Junction-to-board thermal resistance	11.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	11.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

At 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, f_S = 48-kHz, 16-bit audio data (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AUDIO ADC
	Input signal level (0-dB)	Single-ended input			0.707		Vrms
	Input common-mode voltage	Single-ended input			1.35		Vrms
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	f_S = 48 kHz, 0-dB PGA gain, IN1 inputs selected and AC-shorted to ground		80	92		dB
	Dynamic range, A-weighted⁽¹⁾⁽²⁾	f_S = 48 kHz, 1-kHz –60-dB full-scale input applied at IN1 inputs, 0-dB PGA gain			92		dB
THD	Total harmonic distortion	f_S = 48 kHz, 1-kHz –2-dB full-scale input applied at IN1 inputs, 0-dB PGA gain			–90	–75	dB
THD	Total harmonic distortion				0.003%	0.017%
PSRR	Power supply rejection ratio	234 Hz, 100 mV_PP on AVDD, single-ended input			46		dB
PSRR	Power supply rejection ratio	234 Hz, 100 mV_PP on AVDD, differential input			68		dB
	ADC channel separation	1 kHz, –2 dB IN1L to IN1R			–73		dB
	ADC gain error	1 kHz input, 0-dB PGA gain			0.7		dB
	ADC programmable-gain amplifier maximum gain	1-kHz input tone, R_SOURCE < 50 Ω			40		dB
	ADC programmable-gain amplifier step size				0.502		dB
	Input resistance	IN1 inputs, routed to single ADC Input mix attenuation = 0 dB			35		kΩ
		IN2 inputs, input mix attenuation = 0 dB			35
		IN1 inputs, input mix attenuation = –6 dB			62.5
		IN2 inputs, input mix attenuation = –6 dB			62.5
	Input capacitance				10		pF
	Input level control minimum attenuation setting				0		dB
	Input level control maximum attenuation setting				6		dB
	Input level control attenuation step size				6		dB
ADC DIGITAL DECIMATION FILTER		f_S = 48 kHz
	Filter gain from 0 to 0.39 f_S	Filter A, AOSR = 128 or 64			±0.1		dB
	Filter gain from 0.55 f_S to 64 f_S	Filter A, AOSR = 128 or 64			–73		dB
	Filter group delay	Filter A, AOSR = 128 or 64			17/f_S		s
	Filter gain from 0 to 0.39 f_S	Filter B, AOSR = 64			±0.1		dB
	Filter gain from 0.60 f_S to 32 f_S	Filter B, AOSR = 64			–46		dB
	Filter group delay	Filter B, AOSR = 64			11/f_S		s
	Filter gain from 0 to 0.39 f_S	Filter C, AOSR = 32			±0.033		dB
	Filter gain from 0.28 f_S to 16 f_S	Filter C, AOSR = 32			–60		dB
	Filter group delay	Filter C, AOSR = 32			11/f_S		s
MICROPHONE BIAS
	Bias voltage	Programmable settings, load = 750 Ω			2		V
				2.25	2.5	2.75
					AVDD – 0.2
	Current sourcing	2.5-V setting				4	mA
	Integrated noise	BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AGND			3.3		μV rms
DIGITAL I/O
V_IL	Input low level	I_IL = 5 μA		–0.3		0.3 × IOVDD	V
V_IH	Input high level⁽³⁾	I_IH = 5 μA		0.7 × IOVDD			V
V_OL	Output low level	I_IH = 2 TTL loads				0.1 × IOVDD	V
V_OH	Output high level	I_OH = 2 TTL loads		0.8 × IOVDD			V
SUPPLY CURRENT		f_S = 48 kHz, AVDD = 3.3 V, DVDD = IOVDD = 1.8 V
	Mono record	AVDD	PLL and AGC off		2		mA
	Mono record	DVDD	PLL and AGC off		1.9		mA
	Stereo record	AVDD	PLL and AGC off		4		mA
	Stereo record	DVDD	PLL and AGC off		2.1		mA
	PLL	AVDD	Additional power consumed when PLL is powered		1.1		mA
	PLL	DVDD	Additional power consumed when PLL is powered		0.8		mA
	Power down	AVDD	All supply voltages applied, all blocks programmed in lowest power state		0.04		μA
	Power down	DVDD			0.7		μA

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) When IOVDD < 1.6 V, minimum V_IH is 1.1 V.

8.6 Dissipation Ratings⁽¹⁾

PACKAGE TYPE	T_A = 25°C POWER RATING	DERATING FACTOR	T_A = 75°C POWER RATING	T_A = 85°C POWER RATING
VQFN	1.7 W	22 mW/°C	665 mW	444 mW

(1) This data was taken using 2-oz. (0.071-mm thick) trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3-in. × 3-in. (7.62-cm × 7.62-cm) PCB.

8.7 I²S/LJF/RJF Timing in Master Mode

Specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization. See Figure 1 for timing diagram.

		IOVDD = 1.8 V		IOVDD = 3.3 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_d(WS)	BCLK/WCLK delay time		20		15	ns
t_d(DO-WS)	BCLK/WCLK to DOUT delay time		25		20	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		20		15	ns
t_r	Rise time		20		15	ns
t_f	Fall time		20		15	ns

8.8 DSP Timing in Master Mode

Specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization. See Figure 2 for timing diagram.

		IOVDD = 1.8 V		IOVDD = 3.3 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_d(WS)	BCLK/WCLK delay time		25		15	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		25		15	ns
t_r	Rise time		20		15	ns
t_f	Fall time		20		15	ns

8.9 I²S/LJF/RJF Timing in Slave Mode

Specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization. See Figure 3 for timing diagram.

		IOVDD = 1.8 V		IOVDD = 3.3 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_H(BCLK)	BCLK high period	35		35		ns
t_L(BCLK)	BCLK low period	35		35		ns
t_s(WS)	BCLK/WCLK set-up time	10		6		ns
t_h(WS)	BCLK/WCLK hold time	10		6		ns
t_d(DO-WS)	BCLK/WCLK to DOUT delay time (for LJF Mode only)		30		30	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		25		20	ns
t_r	Rise time		16		8	ns
t_f	Fall time		16		8	ns

8.10 DSP Timing in Slave Mode

Specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization. See Figure 4 for timing diagram.

		IOVDD = 1.8 V		IOVDD = 3.3 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_H(BCLK)	BCLK high period	35		35		ns
t_L(BCLK)	BCLK low period	35		35		ns
t_s(WS)	BCLK/WCLK set-up time	10		8		ns
t_h(WS)	BCLK/WCLK hold time	10		8		ns
t_d(DO-BCLK)	BCLK to DOUT delay time		25		20	ns
t_r	Rise time		15		8	ns
t_f	Fall time		15		8	ns