6.1.1 Media Independent Interface (MII)

The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.

The MII signals are summarized below.

Figure 6-1 shows the MII-mode signals.

Figure 6-1 MII Signaling

The Isolate bit (BMCR register bit 10), defined in IEEE802.3-2002, electrically isolates the PHY from the MII (if set, all transactions on the MII interface are ignored by the PHY).

Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both transmit and receive operation occur simultaneously.

6.1.2 Reduced Media Independent Interface (RMII)

TLK10xL incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.

The RMII specification has the following characteristics:

• Supports 10Mbs and 100Mbs data rates
• Single clock reference sourced from the MAC to PHY (or from an external source)
• Provides independent 2 bit wide (di-bit) transmit and receive data paths
• Uses CMOS signal levels, operates at 3.3V or 2.5V VDD_IO levels

In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and receive. RMII mode uses the following pins:

Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks.

In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though not required by RMII spec (The TLK10xL supports optional use of RX_ER and RX_DV in RMII as an extra feature). RMII mode requires a 50MHz oscillator connected to the device XI pin.

The TLK10xL supports a special mode called “RMII receive clock” mode. This mode, which is not part of the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DV and RX_ER signals to this clock. Setting register 0x000A bit [0] is required to activate this mode.

describes the RMII signals connectivity between the TLK10xL and any MAC device.

TLK10xL RMII/MAC Connection

RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy.

indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.

6.1.3 Serial Management Interface

The Serial Management Interface (SMI), provides access to the TLK10xL internal register space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide additional visibility and controllability of the TLK10xL device.

The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.

The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which, during IDLE and turnaround, pulls MDIO high.

Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK10xL latches the PHYAD[4:0] configuration pins (Pin 29 to Pin 32) to determine its address.

The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-asserted.

In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK10xL drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 6-2 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the TLK10xL (PHY) for a typical register read access.

For write transactions, the station-management entity writes data to the addressed TLK10xL, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 6-3 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 6-1, Figure 6-2, and Figure 6-3.

Figure 6-2 Typical MDC/MDIO Read Operation

Figure 6-3 Typical MDC/MDIO Write Operation

The TLK10xL includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up.

At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If required during normal operation, the device can be reset by a hardware or software reset.

6.2.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to RESET. This pulse resets the device such that all registers are reinitialized to default values, and the hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally is approximately 200µs.

6.2.2 Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x0000h). This bit only resets the IEEE-defined standard registers in the address space 0x00h to 0x07h.

A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to ‘1’. This bit resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the extended registers. The global software reset resets the device such that all registers are reset to default values and the hardware configuration values are maintained.

A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to ‘1’. This action resets all the PHY circuits except the registers in the Register File.

The time from the point when the resets/restart bits are set to the point when the software resets/restart has concluded is approximately 200µs. TI recommends that the software driver code must wait 500µs following software reset before allowing further serial MII operations with the TLK10xL.

6.2.3 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed on pin 8 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 0 (INT_OE) to ‘1’ in the PHYSCR (0x0011h) register. The PHYSCR register is also used to enable and set the polarity of the interrupt.

6.2.4 Power Save Modes

The TLK10xL supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available).

To enable and activate all other power save modes through register access, use register PHYSCR (0x0011h). Setting bit 14 enables all power-save modes; bits [13:12] select between them.

Setting bits [13:12] to “01” powers down the PHY, forcing it into IEEE power down mode (Similar to BMCR bit 11 functionality).

Setting bits [13:12] to “10” puts the PHY in Low Power Active Energy Saving mode.

Setting bits [13:12] to “11” puts the PHY in Low Power Passive Energy Saving mode.

When these bits are cleared, the PHY powers up and returns to the last state it was in before it was powered down.

6.3.1 TPI Network Circuit

Figure 6-4 shows the recommended circuit for a 10/100Mbs twisted pair interface. Common mode chokes on the device side of the transformer are required. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.

Figure 6-4 10/100Mbs Twisted Pair Interface

6.3.2 Clock In (XI) Requirements

The TLK10xL supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.

6.3.2.2 Crystal

The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 6-5 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between XO and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for C_L1 and C_L2 at 33pF, and R₁ should be set at 0Ω. Specifications for a 25MHz crystal are listed in Table 6-4.

Figure 6-5 Crystal Oscillator Circuit

Table 6-2 25MHz Oscillator Specification

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			25		MHz
Frequency Tolerance	Operational Temperature			±50	ppm
Frequency Stability	1 year aging			±50	ppm
Rise / Fall Time	10%–90%			8	nsec
Jitter (Short term)	Cycle-to-cycle		50		psec
Jitter (Long term)	Accumulative over 10 ms			1	nsec
Symmetry	Duty Cycle	40%		60%
Load Capacitance			15	30	pF

Table 6-3 50MHz Oscillator Specification

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			50		MHz
Frequency Tolerance	Operational Temperature			±50	ppm
Frequency Stability	1 year aging			±50	ppm
Rise / Fall Time	10%–90%			6	nsec
Jitter (Short term)	Cycle-to-cycle		50		psec
Jitter (Long term)	Accumulative over 10 ms			1	nsec
Symmetry	Duty Cycle	40%		60%

Table 6-4 25MHz Crystal Specification

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			25		MHz
Frequency Tolerance	Operational Temperature			±50	ppm
	At 25°C			±50	ppm
Frequency Stability	1 year aging			±5	ppm
Load Capacitance		10		40	pF

6.3.3 Thermal Vias Recommendation

The following thermal via guidelines apply to DOWN_PAD, pin 33:

1. Thermal via size = 0.2mm
2. Recommend 4 vias
3. Vias have a center to center separation of 2mm.

Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 6-6 illustrates an example layout.

Figure 6-6 Example Layout