SLLSEE3D August 2013 – April 2016 TLK105L , TLK106L
PRODUCTION DATA.
- 1Device Overview
- 2Revision History
- 3Pin Configuration and Functions
-
4Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 ESD Ratings
- 4.3 Recommended Operating Conditions
- 4.4 20
- 4.5 TLK106L 32-Pin Extended Temperature (105°C) Device Thermal Characteristics
- 4.6 DC Characteristics, VDD_IO
- 4.7 DC Characteristics
- 4.8 Power Supply Characteristics
- 4.9
AC Specifications
- 4.9.1 Power Up Timing
- 4.9.2 Reset Timing
- 4.9.3 MII Serial Management Timing
- 4.9.4 100Mb/s MII Transmit Timing
- 4.9.5 100Mb/s MII Receive Timing
- 4.9.6 100Base-TX Transmit Packet Latency Timing
- 4.9.7 100Base-TX Transmit Packet Deassertion Timing
- 4.9.8 100Base-TX Transmit Timing (tR/F and Jitter)
- 4.9.9 100Base-TX Receive Packet Latency Timing
- 4.9.10 100Base-TX Receive Packet Deassertion Timing
- 4.9.11 10Mbs MII Transmit Timing
- 4.9.12 10Mb/s MII Receive Timing
- 4.9.13 10Base-T Transmit Timing (Start of Packet)
- 4.9.14 10Base-T Transmit Timing (End of Packet)
- 4.9.15 10Base-T Receive Timing (Start of Packet)
- 4.9.16 10Base-T Receive Timing (End of Packet)
- 4.9.17 10Mb/s Jabber Timing
- 4.9.18 10Base-T Normal Link Pulse Timing
- 4.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
- 4.9.20 100Base-TX Signal Detect Timing
- 4.9.21 100Mbs Loopback Timing
- 4.9.22 10Mbs Internal Loopback Timing
- 4.9.23 RMII Transmit Timing
- 4.9.24 RMII Receive Timing
- 4.9.25 Isolation Timing
-
5Detailed Description
- 5.1 Hardware Configuration
- 5.2
Architecture
- 5.2.1 100Base-TX Transmit Path
- 5.2.2
100Base-TX Receive Path
- 5.2.2.1 Analog Front End
- 5.2.2.2 Adaptive Equalizer
- 5.2.2.3 Baseline Wander Correction
- 5.2.2.4 NRZI and MLT-3 Decoding
- 5.2.2.5 Descrambler
- 5.2.2.6 5B/4B Decoder and Nibble Alignment
- 5.2.2.7 Timing Loop and Clock Recovery
- 5.2.2.8 Phase-Locked Loops (PLL)
- 5.2.2.9 Link Monitor
- 5.2.2.10 Signal Detect
- 5.2.2.11 Bad SSD Detection
- 5.2.3 10Base-T Receive Path
- 5.2.4 Auto Negotiation
- 5.2.5 Link Down Functionality
- 5.2.6 IEEE 1588 Precision Timing Protocol Support
- 5.3
Register Maps
- 5.3.1
Register Definition
- 5.3.1.1 Basic Mode Control Register (BMCR)
- 5.3.1.2 Basic Mode Status Register (BMSR)
- 5.3.1.3 PHY Identifier Register 1 (PHYIDR1)
- 5.3.1.4 PHY Identifier Register 2 (PHYIDR2)
- 5.3.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 5.3.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 5.3.1.7 Auto-Negotiate Expansion Register (ANER)
- 5.3.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 5.3.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 5.3.1.10 Control register 1 (CR1)
- 5.3.1.11 Control register 2 (CR2)
- 5.3.1.12 Control Register 3 (CR3)
- 5.3.1.13 Extended Register Addressing
- 5.3.1.14 Fast Link Down Status Register
- 5.3.1.15 PHY Status Register (PHYSTS)
- 5.3.1.16 PHY Specific Control Register (PHYSCR)
- 5.3.1.17 MII Interrupt Status Register 1 (MISR1)
- 5.3.1.18 MII Interrupt Status Register 2 (MISR2)
- 5.3.1.19 False Carrier Sense Counter Register (FCSCR)
- 5.3.1.20 Receiver Error Counter Register (RECR)
- 5.3.1.21 BIST Control Register (BISCR)
- 5.3.1.22 RMII Control and Status Register (RCSR)
- 5.3.1.23 LED Control Register (LEDCR)
- 5.3.1.24 PHY Control Register (PHYCR)
- 5.3.1.25 10Base-T Status/Control Register (10BTSCR)
- 5.3.1.26 BIST Control and Status Register 1 (BICSR1)
- 5.3.1.27 BIST Control and Status Register2 (BICSR2)
- 5.3.2 Cable Diagnostic Control Register (CDCR)
- 5.3.3 PHY Reset Control Register (PHYRCR)
- 5.3.4 Multi LED Control register (MLEDCR)
- 5.3.5 Compliance Test register (COMPTR)
- 5.3.6 IEEE1588 Precision Timing Pin Select (PTPPSEL)
- 5.3.7 IEEE1588 Precision Timing Configuration (PTPCFG)
- 5.3.8 TX_CLK Phase Shift Register (TXCPSR)
- 5.3.9 Power Back Off Control Register (PWRBOCR)
- 5.3.10 Voltage Regulator Control Register (VRCR)
- 5.3.11
Cable Diagnostic Configuration/Result Registers
- 5.3.11.1 ALCD Control and Results 1 (ALCDRR1)
- 5.3.11.2 Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
- 5.3.11.3 Cable Diagnostic Location Results Register 1 (CDLRR1)
- 5.3.11.4 Cable Diagnostic Location Results Register 2 (CDLRR2)
- 5.3.11.5 Cable Diagnostic Location Results Register 3 (DDLRR3)
- 5.3.11.6 Cable Diagnostic Location Results Register 4 (CDLRR4)
- 5.3.11.7 Cable Diagnostic Location Results Register 5 (CDLRR5)
- 5.3.11.8 Cable Diagnostic Amplitude Results Register 1 (CDARR1)
- 5.3.11.9 Cable Diagnostic Amplitude Results Register 2 (CDARR2)
- 5.3.11.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
- 5.3.11.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
- 5.3.11.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
- 5.3.11.13 Cable Diagnostic General Results Register (CDGRR)
- 5.3.11.14 ALCD Control and Results 2 (ALCDRR2)
- 5.3.11.15 ALCD Control and Results 3 (ALCDRR3)
- 5.3.1
Register Definition
- 6Applications, Implementation, and Layout
- 7Device and Documentation Support
- 8Mechanical Packaging and Orderable Information
1 Device Overview
1.1 Features
- Low-Power Consumption:
- Single Supply: <205 mW PHY, 275 mW With Center Tap (Typical)
- Dual Supplies: <126 mW PHY, 200 mW With Center Tap (Typical)
- Programmable Power Back Off to Reduce PHY Power up to 20% in Systems With Shorter Cables
- IEEE 1588 SFD Indication Enables Time Stamping by a Controller or Processor
- Low Deterministic Latency Supports IEEE1588 Implementation
- Cable Diagnostics
- Programmable Fast Link Down Modes, <10 µs Reaction Time
- Variable I/O voltage range: 3.3V, 2.5V, 1.8V
- MAC Interface I/O voltage range:
- MII I/O voltage range: 3.3V, 2.5V, 1.8V
- RMII I/O voltage range: 3.3V, 2.5V
- Fixed TX Clock to XI, With Programmable Phase Shift
- Auto-MDIX for 10/100Mbs
- Energy Detection Mode
- MII and RMII Capabilities
- IEEE 802.3u MII
- Error-Free 100Base-T Operation up to 150 Meters Under Typical Conditions
- Error-Free 10Base-T Operation up to 300 Meters Under Typical Conditions
- Serial Management Interface
- IEEE 802.3u Auto-Negotiation and Parallel Detection
- IEEE 802.3u ENDEC, 10Base-T Transceivers and Filters
- IEEE 802.3u PCS, 100Base-TX Transceivers
- Integrated ANSI X3.263 Compliant TP-PMD Physical Sublayer with Adaptive Equalization and Baseline Wander Compensation
- Programmable LED Support Link, Activity
- 10/100Mbs Packet BIST (Built in Self Test)
- HBM ESD Protection on RD± and TD± of 16 kV
- 32-pin VQFN (5 mm) × (5 mm)
1.2 Applications
- Industrial Networks and Factory Automation
- Motor and Motion Control
- General Embedded Applications
1.3 Description
The TLK10xL is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling, integrating all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The device supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC).
The device is designed for power-supply flexibility, and can operate with a single 3.3-V power supply or with combinations of 3.3-V and 1.55-V power supplies for reduced power operation.
The TLK10xL uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. The TLK10xL not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.
The TLK10xL Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100-m cable length, or the extended 150m, error-free cable reach of the TLK10xL. For more detail, see application note SLLA328.
1.4 Functional Block Diagram
Figure 1-1 TLK10xL Functional Block Diagram