ZHCSNE3 June 2021 TLIN2022A-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Power Supply | ||||||
| VSUP | Operational supply voltage (ISO/DIS 17987 Param 10, 53) | Device is operational beyond the LIN defined nominal supply voltage range See Figure 8-1 and Figure 8-2 | 4 | 48 | V | |
| VSUP | Nominal supply voltage (ISO/DIS 17987 Param 10, 53) |
Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHZ square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 | 4 | 48 | V | |
| Sleep Mode | 4 | 48 | V | |||
| UVSUP | Undervoltage VSUP threshold | 2.9 | 3.85 | V | ||
| UVHYS | Delta hysteresis voltage for VSUP undervoltage threshold | 0.2 | V | |||
| ISUP | Supply current | Normal Mode: EN = High, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 1.2 | 8.5 | mA | |
| Standby Mode: EN = Low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 1.1 | 3.75 | mA | |||
| ISUP | Supply current | Normal Mode: EN = High, Bus Recessive: LIN = VSUP | 670 | 1600 | μA | |
| Standby Mode: EN = Low, Bus Recessive LIN = VSUP | 20 | 40 | μA | |||
| Sleep Mode: 4.0 V < VSUP < 14 V, LIN = VSUP, EN = 0 V, TXD and RXD Floating | 10 | 20 | μA | |||
| Sleep Mode: 14 V < VSUP < 36 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 30 | μA | ||||
| RXD1/RXD2 OUTPUT PIN (OPEN DRAIN) | ||||||
| VOL | Output Low voltage | Based upon external pull-up to VCC (4) | 0.6 | V | ||
| IOL | Low-level output current, open-drain | LIN = 0 V, RXD = 0.4 V | 1.5 | mA | ||
| IILG | Leakage current, high-level | LIN = VSUP, RXD = 5 V | –5 | 0 | 5 | μA |
| TXD1/TXD2 INPUT PIN | ||||||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VIH | High-level input voltage | 2 | 5.25 | V | ||
| VHYS | Input threshold voltage, normal modes& selective wake modes | 50 | 500 | mV | ||
| IILG | Low-level input leakage current | TXD = Low | –5 | 0 | 5 | μA |
| RTXD | Internal pull-down resitor value | 125 | 350 | 800 | kΩ | |
| EN1/EN2 INPUT PIN | ||||||
| VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
| VIH | High-level input voltage | 2 | 5.25 | V | ||
| VHYS | Hysteresis voltage | By design and characterization | 50 | 500 | mV | |
| IILG | Low-level input current | EN = Low | –5 | 0 | 5 | μA |
| REN | Internal pull-down resistor | 125 | 350 | 800 | kΩ | |
| LIN1/LIN2 PIN | ||||||
| VOH | HIGH level output voltage (3) | LIN recessive, TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 48 V | 0.85 | VSUP | ||
| VOH | LIN recessive high-level output voltage (1) (2) | TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 18 V | 0.8 | VSUP | ||
| VOH | HIGH level output voltage(3) | LIN recessive, TXD = high, IO = 0 mA, 4 V ≤ VSUP < 7 V | 3 | V | ||
| VOL | LOW level output voltage(3) | LIN dominant, TXD = low, 7 V ≤ VSUP ≤ 48 V | 0.2 | VSUP | ||
| VOL | LIN dominant low- level output voltage (1) (2) | TXD = low, 7 V ≤ VSUP ≤ 18 V | 0.2 | VSUP | ||
| VOL | LOW level output voltage(3) | LIN dominant, TXD = low, 4 V ≤ VSUP < 7 V | 1.2 | V | ||
| VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 56) | TXD & RXD open LIN = 4 V to 58 V | –0.3 | 58 | V | |
| IBUS_LIM | Limiting current (ISO/DIS 17987 Param 57) | TXD = 0 V, VLIN = 48 V, RMEAS = 440 Ω, VSUP = 48 V, VBUSdom < 4.518 V | 75 | 120 | 300 | mA |
| IBUS_PAS_dom | Receiver leakage current, dominant (ISO/DIS 17987 Param 58) | LIN = 0 V, VSUP = 24 V Driver off/recessive; See Figure 8-6 | –2 | mA | ||
| IBUS_PAS_rec1 | Receiver leakage current, recessive (ISO/DIS 17987 Param 59) | LIN > VSUP, 8 V ≤ VSUP ≤ 48 V Driver off; See Figure 8-7 | 20 | μA | ||
| IBUS_PAS_rec2 | Receiver leakage current, recessive (ISO/DIS 17987 Param 59) | LIN = VSUP, Driver off; See Figure 8-7 | –5 | 5 | μA | |
| IBUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 60) | GND = VSUP, 0 V ≤ VLIN = 36 V, VSUP = 24 V; See Figure 8-8 | –2 | 2 | mA | |
| Ileak gnd(dom) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = dominant |
-1 | 1 | mA | |
| Ileak gnd(rec) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = recessive |
-100 | 100 | μA | |
| IBUS_NO_BAT | Leakage current, loss of supply (ISO/DIS 17987 Param 61) | 0 V ≤ VLIN ≤ 48 V, VSUP = GND; See Figure 8-9 | 5 | μA | ||
| VBUSdom | Low-level input voltage (ISO/DIS 17987 Param , 62) | LIN dominant (including LIN dominant for wake up); See Figure 8-3 and Figure 8-4 | 0.4 | VSUP | ||
| VBUSrec | High-level input voltage (ISO/DIS 17987 Param , 63) | LIN recessive; See Figure 8-3 and Figure 8-4 | 0.6 | VSUP | ||
| VIH | LIN recessive high-level input voltage (1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.47 | 0.6 | VSUP | |
| VIL | LIN dominant low-level input voltage (1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.4 | 0.53 | VSUP | |
| VBUS_CNT | Receiver center threshold (ISO/DIS 17987 Param , 64) | VBUS_CNT = ( VBUSdom + VBUSrec )/2; See Figure 8-3 and Figure 8-4 | 0.475 | 0.5 | 0.525 | VSUP |
| VHYS | Hysteresis voltage (ISO/DIS 17987 Param , 65) | VHYS = (VBUSrec - VBUSdom); See Figure 8-3 and Figure 8-4 | 0.175 | VSUP | ||
| VHYS | Hysteresis voltage (SAE J2602) | VHYS = VIH - VIL ; See Figure 8-3 and Figure 8-4 | 0.07 | 0.175 | VSUP | |
| VSERIAL_DIODE | Serial diode LIN termination pullup path (ISO/DIS 17987 Param , 66) | ISERIAL_DIODE = 10 μA | 0.4 | 0.7 | 1 | V |
| RPU | Pull-up resistor to VSUP (ISO/DIS 17987 Param , 71) | Normal and Standby modes | 20 | 45 | 60 | kΩ |
| IRSLEEP | Pull-up current source to VSUP | Sleep mode, VSUP = 27 V, LIN = GND | –20 | –2 | μA | |
| CLINPIN | Capacitance of the LIN pin | VSUP = 14 V | 25 | pF | ||