ZHCSNE3 June 2021 TLIN2022A-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 說明（續(xù)）
- 5 Revision History
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 LIN (Local Interconnect Network) Bus
- 9.3.2 TXD
- 9.3.3 RXD (Receive Output)
- 9.3.4 VSUP (Supply Voltage)
- 9.3.5 GND (Ground)
- 9.3.6 EN (Enable Input)
- 9.3.7 Protection Features
- 9.3.8 TXD Dominant Time Out (DTO)
- 9.3.9 Bus Stuck Dominant System Fault: False Wake-Up Lockout
- 9.3.10 Thermal Shutdown
- 9.3.11 Undervoltage on VSUP
- 9.3.12 Unpowered Device and LIN Bus
- 9.4 Device Functional Modes
- 10Application Information Disclaimer
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DMT|14
訂購信息
8 Parameter Measurement Information
Figure 8-1 Test System: Operating Voltage
Range with RX and TX Access: Parameters 9, 10
Figure 8-2 RX Response: Operating Voltage
Range
Figure 8-3 LIN Bus Input Signal
Figure 8-4 LIN Receiver Test with RX
access Parameters 17, 18, 19, 20
Figure 8-5 VSUP_NON_OP
Parameters 11
Figure 8-6 Test Circuit for
IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V,
Parameters 13
Figure 8-7 Test Circuit for
IBUS_PAS_rec Param 14
Figure 8-8 Test Circuit for
IBUS_NO_GND Loss of GND
Figure 8-9 Test Circuit for
IBUS_NO_BAT Loss of Battery
Figure 8-10 Test Circuit Slope Control and
Duty Cycle Parameters 27, 28, 29, 30
Figure 8-11 Definition of Bus Timing
Parameters
Figure 8-12 Propagation Delay Test
Circuit; Parameters 31, 32
Figure 8-13 Propagation Delay
Figure 8-14 Mode Transitions
Figure 8-15 Wakeup Through EN
Figure 8-16 Wakeup through LIN