ZHCSM81A October 2020 – December 2020 TLC6C5748-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Terminal Configurations and Functions
- 6 Specifications
- 7 Parameter Measurement Information
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8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.4.1 Conventional PWM Control
The first GS clock rising edge increments the GS counter by one and switches on all outputs with a non-zero GS value programmed into the GS data latch. Each additional GS clock rising edge increases the corresponding GS counter by one.
The GS counter keeps track of the number of clock pulses from the respective GS clock inputs. Each output stays on while the counter is less than or equal to the programmed GS value. Each output turns off at the GS counter value rising edge when the counter becomes greater than the output GS latch value. Figure 8-7 illustrates the conventional PWM operation.
Figure 8-7 Conventional PWM Operation