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ZHCSGR5 September 2017 TIC12400

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DCP|38
- MPDS520B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

DCP|38
- PPTD170A

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	V_S, INT	-0.3	40	V
	V_DD, SCLK, SI, SO, CS, RESET	-0.3	6	V
	IN0- IN23	-24	40	V
	CAP_Pre	-0.3	5.5	V
	CAP_A	-0.3	5.5	V
	CAP_D	-0.3	2	V
Operating junction temperature, T_J, V_S = 18 V		-40	125	°C
Operating junction temperature, T_J, V_S = 24 V		-40	95	°C
Storage temperature, T_stg		-55	155	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±2000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Pins IN0-IN23⁽²⁾	±4000
		Charged-device model (CDM), per JEDEC specification JESD-C101⁽¹⁾	All pins	±500
			Corner pins (pin 1, 19, 20 and 38)	±750
		Contact discharge per IEC61000-4-2 contact discharge ⁽³⁾⁽⁴⁾	Pins IN0-IN23v	±8000

(1) JEDEC document JEP155 that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary if precautions are taken.

(2) ±4kV rating on pins IN0-IN23 are stressed with respect to GND (with AGND, DGND, and EP tied together).

(3) External components: capacitor = 15 nF; resistor = 33 Ω

(4) ESD generator parameters: storage capacitance = 150 pF or 330pF; discharge resistance = 330 Ω or 2000 Ω

6.3 Recommended Operating Conditions

over operating free-air temperature range and V_S = 12 V (unless otherwise noted)

		MIN	MAX	UNIT
V_S	Power supply voltage, T_A = -40 °C to 105 °C	6.5	18	V
V_S	Power supply voltage, T_A = -40 °C to 85 °C	6.5	24	V
V_DD	Logic supply voltage	3.0	5.5	V
V_/INT	INT pin voltage	0	35	V
V_INX	IN0 to IN23 input voltage	0	35	V
V_RESET	RESET pin voltage	0	5.5	V
V_{SPI_IO}	SPI input/output logic level	0	V_DD	V
f_SPI	SPI communication frequency	20⁽¹⁾	4M	Hz
T_A	Operating free-air temperature, VS = 18 V	-40	102	°C
T_A	Operating free-air temperature, VS = 24 V	-40	85	°C

(1) Lowest frequency characterized.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TIC10024-Q1	UNIT
		DCP (TSSOP)
		38 PINS
R_θJA	Junction-to-ambient thermal resistance	33.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.4	°C/W
R_θJB	Junction-to-board thermal resistance	15.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	15.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range, V_S = 6.5 V to 35 V, and V_DD = 3 V to 5.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
I_{S_CONT}	Continuous mode V_S power supply current	Continuous mode, I_WETT= 10 mA, all switches open, no active comparator operation, no unserviced interrupt			5.6	7	mA
I_{S_POLL_COMP_25}	Polling mode V_S power supply average current	T_A= 25°	Polling mode, t_POLL= 64 ms, t_POLL_ACT= 128 µs, all switches open, I_WETT= 10 mA, no unserviced interrupt		68	100	µA
I_{S_POLL_COMP_85}		T_A= -40° to 85°C			68	110	µA
I_{S_POLL_COMP}		T_A= -40° to 105°C			68	170	µA
I_{S_RESET}	Reset mode V_S power supply current	Reset mode, V_RESET= V_DD. V_S= 12 V, all switches open, T_A=25°C			12	17	µA
I_{S_IDLE_25}	V_S power supply average current in idle state	TRIGGER bit in CONFIG register = logic 0, T_A= 25°C, no unserviced interrupt			50	75	µA
I_{S_IDLE_85}		TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 85°C, no unserviced interrupt			50	95	µA
I_{S_IDLE}		TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 125°C, no unserviced interrupt			50	145	µA
I_DD	Logic supply current from V_DD	SCLK = SI = 0 V, CS = INT = V_DD, no SPI communication			1.5	10	µA
V_{POR_R}	Power on reset (POR) voltage for V_S	Threshold for rising V_S from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register		3.85		4.5	V
V_{POR_F}	Power on reset (POR) voltage for V_S	Threshold for falling V_S from device normal operation to reset mode and loss of SPI communication		1.95		2.8	V
V_{OV_R}	Over-voltage (OV) condition for V_S	Threshold for rising V_S from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register		35		40	V
V_{OV_HYST}	Over-voltage (OV) condition hysteresis for V_S			1		3.5	V
V_{UV_R}	Under-voltage (UV) condition for V_S	Threshold for rising V_S from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register		3.85		4.5	V
V_{UV_F}	Under-voltage (UV) condition for V_S	Threshold for falling V_S from under-votlage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register		3.7		4.4	V
V_{UV_HYST}	Under-voltage (UV) condition hysteresis for V_S⁽¹⁾			75		275	mV
V_{DD_F}		Threshold for falling V_DD resulting in loss of SPI communication		2.5		2.9	V
V_{DD_HYST}	Valid V_DD voltage hysteresis			50		150	mV
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω)
I_WETT (CSO)	Wetting current accuracy for CSO (switch closed)	1 mA setting	6.5 V ≤ V_S ≤ 35 V	0.84	1	1.14	mA
		2 mA setting		1.71	2	2.32
		5 mA setting		4.3	5	5.6
		10 mA setting		8.4	10	11.4
		15 mA setting		12.5	15	17
I_WETT (CSI)	Wetting current accuracy for CSI (switch closed)	1 mA setting		0.75	1.1	2.05
		2 mA setting		1.6	2.2	3.3
		5 mA setting		4.3	5.6	7.1
		10 mA setting		9.2	11.5	13.4
		15 mA setting		13.7	16.5	19.2
V_{CSI_DROP_OPEN}	Voltage drop from IN_x pin to AGND across CSI (switch open)	10 mA setting, R_SW= 5kΩ	6.5 V ≤ V_S ≤ 35V			1.7	V
V_{CSI_DROP_OPEN}	Voltage drop from IN_x pin to AGND across CSI (switch open)	15 mA setting, R_SW= 5kΩ	6.5 V ≤ V_S ≤ 35V			1.7	V
V_{CSI_DROP_CLOSED}	Voltage drop from INx pin to ground across CSI (switch closed)	2mA setting, I_IN= 1mA	6.5 V ≤ V_S ≤ 35V			1.2	V
		5mA setting, I_IN= 1mA or 2mA				1.3	V
		10mA setting, I_IN= 1mA, 2mA, or 5mA				1.5	V
		15mA setting, I_IN= 1mA, 2mA, 5mA, or 10mA				2.1	V
LEAKAGE CURRENTS
I_{IN_LEAK_OFF}	Leakage current at input INx when channel is disabled	0 V ≤ V_INx ≤ V_S , channel disabled (EN_INx register bit= logic 0)		-4		5.3	µA
I_{IN_LEAK_OFF_25}	Leakage current at input INx when channel is disabled	0 V ≤ V_INx ≤ V_S , channel disabled (EN_INx register bit= logic 0), T_A = 25°C		-0.5		0.5	µA
I_{IN_LEAK_0mA}	Leakage current at input INx when wetting current setting is 0mA	0 V ≤ V_INx ≤ 6 V, 6.5 V ≤ V_S ≤ 35 V , I_WETT setting = 0 mA		-110		110	µA
I_{IN_LEAK_0mA}				-110		110	µA
I_{IN_LEAK_LOSS_OF_GND}	Leakage current at input INx under loss of GND condition	V_S = 24 V, 0 V ≤ V_INx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, V_DD shorted to the grounds⁽¹⁾		-5			µA
I_{IN_LEAK_LOSS_OF_VS}	Leakage current at input INx under loss of V_S condition	0 V ≤ V_INx ≤ 24 V, V_S shorted to the grounds = 0 V, V_DD = 0 V				5	µA
LOGIC LEVELS
V_{/INT_L}	INT output low voltage	I_/INT = 2 mA				0.35	V
V_{/INT_L}	INT output low voltage	I_/INT = 4 mA				0.6	V
V_{SO_L}	SO output low voltage	I_SO = 2 mA				0.2V_DD	V
V_{SO_H}	SO output high voltage	I_SO = -2 mA		0.8V_DD			V
V_{IN_L}	SI, SCLK, and CS input low voltage					0.3V_DD	V
V_{IN_H}	SI, SCLK, and CS input high voltage			0.7V_DD			V
V_{RESET_L}	RESET input low voltage					0.8	V
V_{RESET_H}	RESET input high voltage			1.6			V
R_{RESET_25}	RESET pin internal pull-down resistor	V_RESET= 0 to 5.5V, T_A= 25°C		0.85	1.25	1.7	MΩ
R_RESET	RESET pin internal pull-down resistor	V_RESET = 0 to 5.5V, T_A= –40° to 105°C		0.2		2.1	MΩ
COMPARATOR PARAMETERS
V_{TH_ COMP_2V}	Comparator threshold for 2 V	THRES_COMP = 2 V		1.85		2.25	V
V_{TH_ COMP_2p7V}	Comparator threshold for 2.7 V	THRES_COMP = 2.7 V		2.4		2.9	V
V_{TH_ COMP_3V}	Comparator threshold for 3 V	THRES_COMP = 3 V		2.85		3.3	V
V_{TH_ COMP_4V}	Comparator threshold for 4 V	THRES_COMP = 4 V		3.7		4.35	V
R_{IN, COMP}	Comparator equivalent input resistance	THRES_COMP = 2 V		30	130		kΩ
		THRES_COMP = 2.7 V		35	130
		THRES_COMP = 3 V		35	105
		THRES_COMP = 4 V		43	95

(1) Specified by design.

6.6 Timing Requirements

V_S= 6.5 V to 35 V, V_DD= 3 V to 5.5 V, and 10 pF capacitive load on SO unless otherwise noted; verified by design and characterization

			MIN	NOM	MAX	UNIT
SWITCH MONITORING, INTERRUPT, STARTUP AND RESET
t_{POLL_ACT}	Polling active time accuracy	Polling mode	-12%		12%
t_POLL	Polling time accuracy	Polling mode	-12%		12%
t_COMP	Comparator detection time			18		µs
t_{CCP_TRAN}	Transition time between last input sampling and start of clean current			20		µs
t_{CCP_ACT}	Clean current active time		-12%		12%
t_STARTUP	Polling startup time		200	300	400	µs
t_{INT_ACTIVE}	Active INT assertion duration		1.5	2	2.5	ms
t_{INT_INACTIVE}	INT de-assertion duration during a pending interrupt		3	4	5	ms
t_{INT_IDLE}	Interrupt idle time		80	100	120	µs
t_RESET	Time required to keep the RESET pin high to successfully reset the device (no pending interrupt)⁽¹⁾		2			µs
t_REACT	Delay between a fault event (OV, UV, TW, or TSD) to a high to low transition on the INT pin	See Figure 10 for OV example.			20	µs
SPI INTERFACE
t_LEAD	Falling edge of CS to rising edge of SCLK setup time		100			ns
t_LAG	Falling edge of SCLK to rising edge of CS setup time		100			ns
t_SU	SI to SCLK falling edge setup time		30			ns
t_HOLD	SI hold time after falling edge of SCLK		20			ns
t_VALID	Time from rising edge of SCLK to valid SO data				70	ns
t_SO(EN)	Time from falling edge of CS to SO low-impedance				60	ns
t_SO(DIS)	Time from rising edge of CS to SO high-impedance	Loading of 1 kΩ to GND. See Figure 11.			60	ns
t_R	SI, CS, and SCLK signals rise time			5	30	ns
t_F	SI, CS, and SCLK signals fall time			5	30	ns
t_{INTER_FRAME}	Delay between two SPI communication (CS low) sequences		1.5			µs
t_CKH	SCLK High time		120			ns
t_CKL	SCLK Low time		120			ns
t_INITIATION	Delay between valid V_DD voltage and initial SPI communication		45			µs