ZHCSGR5 September 2017 TIC12400
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VS Pin
- 8.3.2 VDD Pin
- 8.3.3 Device Initialization
- 8.3.4 Device Trigger
- 8.3.5 Device Reset
- 8.3.6 VS Under-Voltage (UV) Condition
- 8.3.7 VS Over-Voltage (OV) Condition
- 8.3.8 Switch inputs Settings
- 8.3.9 Interrupt Generation and INT Assertion
- 8.3.10 Temperature Monitor
- 8.3.11 Parity Check And Parity Generation
- 8.3.12 Cyclic Redundancy Check (CRC)
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 DEVICE_ID register (Offset = 1h) [reset = 20h]
- 8.6.2 INT_STAT Register (Offset = 2h) [reset = 1h]
- 8.6.3 CRC Register (Offset = 3h) [reset = FFFFh]
- 8.6.4 IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
- 8.6.5 IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
- 8.6.6 IN_STAT_ADC0 Register (Offset = 6h) [reset = 0h]
- 8.6.7 IN_STAT_ADC1 Register (Offset = 7h) [reset = 0h]
- 8.6.8 IN_STAT_MATRIX0 Register (Offset = 8h) [reset = 0h]
- 8.6.9 IN_STAT_MATRIX1 Register (Offset = 9h) [reset = 0h]
- 8.6.10 ANA_STAT0 Register (Offset = Ah) [reset = 0h]
- 8.6.11 ANA_STAT1 Register (Offset = Bh) [reset = 0h]
- 8.6.12 ANA_STAT2 Register (Offset = Ch) [reset = 0h]
- 8.6.13 ANA_STAT3 Register (Offset = Dh) [reset = 0h]
- 8.6.14 ANA_STAT4 Register (Offset = Eh) [reset = 0h]
- 8.6.15 ANA_STAT5 Register (Offset = Fh) [reset = 0h]
- 8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]
- 8.6.17 ANA_STAT7 Register (Offset = 11h) [reset = 0h]
- 8.6.18 ANA_STAT8 Register (Offset = 12h) [reset = 0h]
- 8.6.19 ANA_STAT9 Register (Offset = 13h) [reset = 0h]
- 8.6.20 ANA_STAT10 Register (Offset = 14h) [reset = 0h]
- 8.6.21 ANA_STAT11 Register (Offset = 15h) [reset = 0h]
- 8.6.22 ANA_STAT12 Register (Offset = 16h) [reset = 0h]
- 8.6.23 CONFIG Register (Offset = 1Ah) [reset = 0h]
- 8.6.24 IN_EN Register (Offset = 1Bh) [reset = 0h]
- 8.6.25 CS_SELECT Register (Offset = 1Ch) [reset = 0h]
- 8.6.26 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
- 8.6.27 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
- 8.6.28 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
- 8.6.29 CCP_CFG1 Register (Offset = 20h) [reset = 0h]
- 8.6.30 THRES_COMP Register (Offset = 21h) [reset = 0h]
- 8.6.31 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
- 8.6.32 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
- 8.6.33 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
- 8.6.34 INT_EN_CFG1 Register (Offset = 25h) [reset = 0h]
- 8.6.35 INT_EN_CFG2 Register (Offset = 26h) [reset = 0h]
- 8.6.36 INT_EN_CFG3 Register (Offset = 27h) [reset = 0h]
- 8.6.37 INT_EN_CFG4 Register (Offset = 28h) [reset = 0h]
- 8.6.38 THRES_CFG0 Register (Offset = 29h) [reset = 0h]
- 8.6.39 THRES_CFG1 Register (Offset = 2Ah) [reset = 0h]
- 8.6.40 THRES_CFG2 Register (Offset = 2Bh) [reset = 0h]
- 8.6.41 THRES_CFG3 Register (Offset = 2Ch) [reset = X]
- 8.6.42 THRES_CFG4 Register (Offset = 2Dh) [reset = X]
- 8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [reset = 0h]
- 8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [reset = 0h]
- 8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [reset = 0h]
- 8.6.46 Matrix Register (Offset = 31h) [reset = 0h]
- 8.6.47 Mode Register (Offset = 32h) [reset = 0h]
- 8.7 Programming Guidelines
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
11 Layout
11.1 Layout Guidelines
Figure 88 illustrates an example of a PCB layout with the TIC12400. Some key considerations are:
1. Decouple the VS and VDD pins with capacitor using recommended values from section Power Supply Recommendations , and place them as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the VS and VDD supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary
5. To achieve good thermal performance, the exposed thermal pad underneath the device must be soldered to the board and flooded with VIAs to ground planes. For simple double-sided PCBs where there are no internal layers, the surface layers can be used to remove heat. For multilayer PCBs, internal ground plane can be used for heat removal.
11.2 Layout Example
Figure 88. Example Layout